公开(公告)号：US20200168636A1

公开(公告)日：2020-05-28

申请号：US16631811

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Elijah V. KARPOV

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78

Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the In topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

公开(公告)号：US20200161473A1

公开(公告)日：2020-05-21

申请号：US16633094

申请日：2017-09-17

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Willy RACHMADY ,  Brian S. DOYLE ,  Abhishek A. SHARMA ,  Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.

公开(公告)号：US20190214559A1

公开(公告)日：2019-07-11

申请号：US16099173

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： James S. CLARKE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Tejaswi K. INDUKURI ,  Niloy MUKHERJEE ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  G11C13/0007 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1675

Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.

公开(公告)号：US20190066779A1

公开(公告)日：2019-02-28

申请号：US16080922

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Niloy MUKHERJEE ,  Uday SHAH

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/73 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2445

Abstract: One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.

公开(公告)号：US20190043868A1

公开(公告)日：2019-02-07

申请号：US16011129

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Khaled HASNAT ,  Prashant MAJHI

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/06 ,  H01L23/522 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: Three-dimensional (3D) memory with control the array and control circuitry in separately processed and bonded wafers is described. In one example, a non-volatile storage component includes a first die including a three-dimensional (3D) array of non-volatile storage cells and a second die bonded with the first die. The second die includes CMOS (complementary metal oxide semiconductor) circuitry to access the 3D array of non-volatile storage cells. By processing the CMOS circuitry and array on separate wafers, the periphery CMOS and interconnects do not have to withstand the thermal cycles involved in processing the memory array, which enables optimizations for the CMOS transistors and the use low resistive material for interconnects.

公开(公告)号：US20190043836A1

公开(公告)日：2019-02-07

申请号：US16011139

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Richard FASTOW ,  Khaled HASNAT ,  Prashant MAJHI ,  Owen JUNGROTH

IPC: H01L25/065 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/00

Abstract: Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.

公开(公告)号：US20180204842A1

公开(公告)日：2018-07-19

申请号：US15574092

申请日：2015-06-23

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Jack T. KAVALIEROS ,  Robert S. CHAU ,  Niloy MUKHERJEE ,  Rafael RIOS ,  Prashant MAJHI ,  Van H. LE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Gilbert DEWEY ,  Marko RADOSAVLJEVIC

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/11551 ,  H01L27/1156 ,  H01L29/786 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/108 ,  G11C13/0007 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1214 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L29/7869 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633

Abstract: A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.

公开(公告)号：US20170288140A1

公开(公告)日：2017-10-05

申请号：US15505909

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Niloy MUKHERJEE ,  Prashant MAJHI ,  Robert S. CHAU

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/147 ,  H01L45/16

Abstract: Thin film 1S1R bitcells incorporating a barrier between selector and memory elements. Devices incorporating such bitcells and methods of forming such bitcells are also described. In embodiments, the selector and memory element is each a dielectric material, and advantageously a metal oxide. Between the selector and memory elements is a barrier, which is to reduce intermixing and/or reaction of selector material and memory material. Addition of a barrier layer having suitable material properties into the 1S1R stack may extend the operating lifetime of a bitcell incorporated the stack by resisting intermixing and/or reaction of the selector and memory thin film materials driven by thermal and/or electric field stresses experienced by a bitcell during operation. In embodiments, a barrier layer may include one or more material layers having a composition distinct from the material composition(s) of the selector and memory elements.