公开(公告)号：US09887104B2

公开(公告)日：2018-02-06

申请号：US14323077

申请日：2014-07-03

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Patrick Nardi ,  David Woodhams

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/24 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/24 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83951 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.

公开(公告)号：US20170271270A1

公开(公告)日：2017-09-21

申请号：US15074050

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Anna M. Prakash ,  Joshua D. Heppner ,  Eric J. Li ,  Nachiket R. Raravikar

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.

公开(公告)号：US20170179103A1

公开(公告)日：2017-06-22

申请号：US15450900

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mauro Kobrinsky ,  Johanna Swan ,  Rajendra C. Dias

IPC: H01L25/00 ,  H01L23/00

Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.

公开(公告)号：US20160233175A1

公开(公告)日：2016-08-11

申请号：US14618647

申请日：2015-02-10

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Emre Armagan ,  Rajendra C. Dias ,  Lars D. Skoglund

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/12 ,  H01L21/304 ,  H01L29/06 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/563 ,  H01L23/12 ,  H01L23/3157 ,  H01L29/06 ,  H01L2224/73204

Abstract: A microelectronic die may be formed with chamfer corners for reducing stresses which can lead to delamination and/or cracking failures when such a microelectronic die is incorporated into a microelectronic package. In one embodiment, a microelectronic die may include at least one substantially planar chamfering side extending between at least two adjacent sides of a microelectronic die. In another embodiment, a microelectronic die may include at least one substantially curved or arcuate chamfering side extending between at least two adjacent sides of a microelectronic die.

Abstract translation: 可以形成具有倒角的微电子模具，用于减小当将这种微电子管芯并入微电子封装时可能导致分层和/或破裂故障的应力。 在一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上平面的倒角侧。 在另一个实施例中，微电子管芯可以包括在微电子管芯的至少两个相邻侧面之间延伸的至少一个基本上弯曲或弧形的倒角侧。

公开(公告)号：US08999765B2

公开(公告)日：2015-04-07

申请号：US13925967

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Rajendra C. Dias ,  Yonghao Xiu ,  Arjun Krishnan ,  Yiqun Bai ,  Purushotham Kaushik Muthur Srinath

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L23/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract translation: 本说明书的实施例包括在微电子器件上处理底部填充材料之后，将微电子器件附着到具有互连结构的微电子衬底的方法，其中在将微电子器件连接到底部填充材料之前，底部填充材料内的填料颗粒可能被排除离开互连结构 器件到微电子结构。 这些方法可以包括在互连结构上引入电荷，并且可以包括将互连结构放置在相对的板之间，并且在将底部填充材料沉积在互连结构上之后在相对的板之间产生偏压。

公开(公告)号：US10685949B2

公开(公告)日：2020-06-16

申请号：US15450900

申请日：2017-03-06

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mauro Kobrinsky ,  Johanna Swan ,  Rajendra C. Dias

IPC: H01L25/00 ,  H05K1/14 ,  H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46

Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.

公开(公告)号：US10535615B2

公开(公告)日：2020-01-14

申请号：US15548741

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Srikant Nekkanty ,  Rajendra C. Dias ,  Patrick Nardi

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/498 ,  H01L23/58

Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.

公开(公告)号：US10468357B2

公开(公告)日：2019-11-05

申请号：US15546958

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Tatyana N. Andryushchenko ,  Mauro J. Kobrinsky ,  Aleksandar Aleksov ,  David W. Staines

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: Embodiments of the invention include a microelectronic device and methods for forming a microelectronic device. In an embodiment, the microelectronic device includes a semiconductor die that has one or more die contacts that are each electrically coupled to a contact pad by a conductive trace. The semiconductor die may have a first elastic modulus. The microelectronic device may also include an encapsulation layer over the semiconductor die and the conductive trace. The encapsulation layer may have a second elastic modulus that is less than the first elastic modulus. The microelectronic device may also include a first strain redistribution layer within the encapsulation layer. The first strain redistribution layer may have a footprint that covers the semiconductor die and a portion of the conductive traces. The strain redistribution layer may have a third elastic modulus that is less than the first elastic modulus and greater than the second elastic modulus.

公开(公告)号：US20190157215A1

公开(公告)日：2019-05-23

申请号：US16256338

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Rajendra C. Dias ,  Mitul B. Modi

IPC: H01L23/552 ,  H01L21/285 ,  H01L23/29 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L21/784 ,  H01L21/78 ,  H01L23/544

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

公开(公告)号：US20180033741A1

公开(公告)日：2018-02-01

申请号：US15548741

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Srikant Nekkanty ,  Rajendra C. Dias ,  Patrick Nardi

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/585 ,  H01L2924/3511

Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.