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    Deriving power output from an energy harvester
    21.
    发明授权
    Deriving power output from an energy harvester 有权

    公开(公告)号：US10958163B2

    公开(公告)日：2021-03-23

    申请号：US16820555

    申请日：2020-03-16

    Applicant: Intel Corporation

    Inventor： Lilly Huang ,  Christopher Schaef ,  Vaibhav Vaidya ,  Suhwan Kim

    IPC: H02M3/07 ,  H02M3/158 ,  H02J7/34 ,  H02M1/00

    Abstract: Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

    Reference voltage generation
    24.
    发明授权
    Reference voltage generation 有权

    公开(公告)号：US10720831B2

    公开(公告)日：2020-07-21

    申请号：US15855683

    申请日：2017-12-27

    Applicant: INTEL CORPORATION

    Inventor： Christopher Schaef ,  Vaibhav Vaidya ,  Suhwan Kim

    IPC: H02M3/07 ,  H02M3/28 ,  H03K3/011 ,  H03B5/04

    Abstract: In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.

    Fuse-less self-start controller
    28.
    发明授权
    Fuse-less self-start controller 有权

    公开(公告)号：US11336270B2

    公开(公告)日：2022-05-17

    申请号：US17006726

    申请日：2020-08-28

    Applicant: Intel Corporation

    Inventor： Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Christopher Schaef

    IPC: H03K3/00 ,  H03K3/037 ,  H03K5/24 ,  H03K17/687

    Abstract: A digital self-start controller, which is functional without fuse and/or trim information. The self-start controller protects a DC-DC converter against large inrush currents and voltage overshoots, while being capable of following a variable VID (voltage identification) reference ramp imposed by the system. The self-start controller uses a relaxation oscillator to set the switching frequency of the DC-DC converter. The oscillator can be initialized using either a clock or current reference to be close to a desired operating frequency. The output of the DC-DC converter is coupled weakly to the oscillator to set the duty cycle for closed loop operation. The controller is naturally biased such that the output supply voltage is always slightly higher than a set point, eliminating the need for any process, voltage, and/or temperature (PVT) imposed trims.

    SEAMLESS NON-LINEAR VOLTAGE REGULATION CONTROL TO LINEAR CONTROL APPARATUS AND METHOD
    29.
    发明申请
    SEAMLESS NON-LINEAR VOLTAGE REGULATION CONTROL TO LINEAR CONTROL APPARATUS AND METHOD 有权

    公开(公告)号：US20220069703A1

    公开(公告)日：2022-03-03

    申请号：US17009661

    申请日：2020-09-01

    Applicant: Intel Corporation

    Inventor： Harish Krishnamurthy ,  Sheldon Weng ,  Nachiket Desai ,  Suhwan Kim ,  Fabrice Paillet

    IPC: H02M3/157 ,  H03H17/02 ,  H02M3/158 ,  G06F1/26

    Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

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