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公开(公告)号：US10437318B2
公开(公告)日：2019-10-08
申请号：US14986677
申请日：2016-01-02
Applicant: Intel Corporation
Inventor： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
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公开(公告)号：US10235177B2
公开(公告)日：2019-03-19
申请号：US15201403
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Janghaeng Lee , Youfeng Wu
Abstract: In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.
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公开(公告)号：US10078357B2
公开(公告)日：2018-09-18
申请号：US14594465
申请日：2015-01-12
Applicant: Intel Corporation
Inventor： Jaewoong Chung , Hanjun Kim , Youfeng Wu
CPC classification number: G06F1/3234 , G06F1/3243 , G06F1/3287 , G06F9/30 , G06F9/30083 , G06F9/3836 , Y02D10/152 , Y02D10/171 , Y02D50/20
Abstract: In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed.
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24.发明授权公开(公告)号：US09996356B2
公开(公告)日：2018-06-12
申请号：US14998299
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Oleg Margulis , Jason M. Agron , Ethan Schuchman , Sebastian Winkel , Youfeng Wu , Gisle Dankel
CPC classification number: G06F9/30185 , G06F9/3826 , G06F9/3834 , G06F9/3838 , G06F9/3865
Abstract: Apparatus and method for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.
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公开(公告)号：US20180004524A1
公开(公告)日：2018-01-04
申请号：US15201403
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Janghaeng Lee , Youfeng Wu
IPC: G06F9/30
CPC classification number: G06F9/30123 , G06F8/41 , G06F9/3016 , G06F9/384
Abstract: In an example, there is disclosed an apparatus, including a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. There is also disclosed a processor to reclaim the physical register based at least in part on the reclamation hint.
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Patent Agency Ranking
公开(公告)号：US20170351516A1
公开(公告)日：2017-12-07
申请号：US15175899
申请日：2016-06-07
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Oleg Margulis , Ching-Tsun Chou , Youfeng Wu
IPC: G06F9/30 , G06F9/38 , G06F9/32 , G06F12/0831 , G06F12/0875
CPC classification number: G06F9/30043 , G06F9/3017 , G06F9/327 , G06F9/3842 , G06F9/3851 , G06F9/3855
Abstract: A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.
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公开(公告)号：US09767037B2
公开(公告)日：2017-09-19
申请号：US14751454
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Marcelo S. Cintra , Cheng Wang , Youfeng Wu , Alexandre Xavier DuChateau
IPC: G06F12/10 , G06F12/02 , G06F12/1009
CPC classification number: G06F12/1009 , G06F8/447 , G06F9/3836 , G06F9/44568 , G06F12/0238 , G06F12/0292 , G06F2212/1044
Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses. Other embodiments are described and claimed.
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公开(公告)号：US09690552B2
公开(公告)日：2017-06-27
申请号：US14583657
申请日：2014-12-27
Applicant: Intel Corporation
Inventor： Hongbo Rong , Peng Tu , Tatiana Shpeisman , Hai Liu , Todd A. Anderson , Youfeng Wu , Paul M. Petersen , Victor W. Lee , P. G. Lowney , Arch D. Robison , Cheng Wang
CPC classification number: G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
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公开(公告)号：US09588814B2
公开(公告)日：2017-03-07
申请号：US14582430
申请日：2014-12-24
Applicant: INTEL CORPORATION
Inventor： Sara S. Baghsorkhi , Albert Hartono , Youfeng Wu , Cheng Wang
CPC classification number: G06F9/50 , G06F9/30 , G06F9/3834 , G06F9/3838
Abstract: The present disclosure is directed to fast approximate conflict detection. A device may comprise, for example, a memory, a processor and a fast conflict detection module (FCDM) to cause the processor to perform fast conflict detection. The FCDM may cause the processor to read a first and second vector from memory, and to then generate summaries based on the first and second vectors. The summaries may be, for example, shortened versions of write and read addresses in the first and second vectors. The FCDM may then cause the processor to distribute the summaries into first and second summary vectors, and may then determine potential conflicts between the first and second vectors by comparing the first and second summary vectors. The summaries may be distributed into the first and second summary vectors in a manner allowing all of the summaries to be compared to each other in one vector comparison transaction.
Abstract translation: 本公开涉及快速近似冲突检测。 设备可以包括例如存储器，处理器和快速冲突检测模块（FCDM），以使处理器执行快速冲突检测。 FCDM可以使处理器从存储器读取第一和第二矢量，然后基于第一和第二矢量生成汇总。 摘要可以是例如第一和第二向量中的写入和读取地址的缩写版本。 然后，FCDM可以使处理器将摘要分发到第一和第二摘要向量中，然后可以通过比较第一和第二概括向量来确定第一和第二向量之间的潜在冲突。 总结可以以允许在一个向量比较事务中将所有概要相互比较的方式分发到第一和第二摘要向量中。
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公开(公告)号：US09542211B2
公开(公告)日：2017-01-10
申请号：US14225755
申请日：2014-03-26
Applicant: Intel Corporation
Inventor： Cheng Wang , Youfeng Wu , Hongbo Rong , Hyunchul Park
CPC classification number: G06F9/45516 , G06F9/4411 , G06F9/4552 , G06F13/10
Abstract: In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括至少一个核心和动态语言加速器，以响应于与动态语言加速器相关联的文件描述符的存储器映射的输入/输出（MMIO）操作来执行字节码。 当动态语言加速器执行字节码时，处理器可能会阻止本地代码的执行。 描述和要求保护其他实施例。
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