公开(公告)号：US20150137315A1

公开(公告)日：2015-05-21

申请号：US14599843

申请日：2015-01-19

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

公开(公告)号：US08975633B2

公开(公告)日：2015-03-10

申请号：US13664922

申请日：2012-10-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

Inventor： Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/00 ,  H01L29/12 ,  H01L29/786 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L28/75

Abstract: A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO2 if the dielectric layer is TiO2 in the rutile phase. The other component of the bilayer (i.e. top layer) is a sub-oxide of the same material as the bottom layer. The top layer serves to protect the bottom layer from oxidation during subsequent PMA or other DRAM fabrication steps by reacting with any oxygen species before they can reach the bottom layer of the bilayer second electrode.

Abstract translation: 形成用于MIM DRAM电容器的金属氧化物双层第二电极，其中与电介质层（即，底层）接触的电极层具有期望的组成和晶体结构。 如果电介质层是金红石相中的TiO 2，那么结晶MoO2就是一个例子。 双层的另一部分（即顶层）是与底层相同的材料的次氧化物。 顶层用于在随后的PMA或其它DRAM制造步骤期间通过与任何氧物种反应而在它们可以到达双层第二电极的底层之前保护底层免受氧化。

公开(公告)号：US08836002B2

公开(公告)日：2014-09-16

申请号：US13738794

申请日：2013-01-10

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Karthik Ramani ,  Hanhong Chen ,  Wim Deweerd ,  Nobumichi Fuchigami ,  Hiroyuki Ode

IPC: H01L27/108 ,  H01L29/94 ,  H01G4/12 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01G4/1218 ,  H01G4/33 ,  H01L28/60 ,  H01L28/75 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO2) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO2 is used as the dielectric layer. The rutile-phase of TiO2 has a higher k value than the other possible crystal structures of TiO2 resulting in improved performance of the DRAM capacitor.

公开(公告)号：US08652927B2

公开(公告)日：2014-02-18

申请号：US13738510

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

IPC: H01L21/20

CPC classification number: H01L29/92 ,  H01L28/75 ,  H01L28/92

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电极结构由多种材料构成。 在基板上方形成第一材料。 蚀刻第一材料的一部分。 在第一材料上方形成第二材料。 蚀刻第二材料的一部分。 可选地，第一电极结构接受退火处理。 介电材料形成在第一电极结构之上。 可选地，电介质材料接受退火处理。 在电介质材料上方形成第二电极材料。 通常，电容器堆叠接收退火处理。

公开(公告)号：US20130320495A1

公开(公告)日：2013-12-05

申请号：US13738510

申请日：2013-01-10

Applicant: INTERMOLECULAR, INC.

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

IPC: H01L29/92

CPC classification number: H01L29/92 ,  H01L28/75 ,  H01L28/92

Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电极结构由多种材料构成。 在基板上方形成第一材料。 蚀刻第一材料的一部分。 在第一材料上方形成第二材料。 蚀刻第二材料的一部分。 可选地，第一电极结构接受退火处理。 介电材料形成在第一电极结构之上。 可选地，电介质材料接受退火处理。 在电介质材料上方形成第二电极材料。 通常，电容器堆叠接收退火处理。

公开(公告)号：US20130140619A1

公开(公告)日：2013-06-06

申请号：US13738866

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

公开(公告)号：US20130122683A1

公开(公告)日：2013-05-16

申请号：US13738865

申请日：2013-01-10

Applicant: Intermolecular Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

公开(公告)号：US20130119512A1

公开(公告)日：2013-05-16

申请号：US13665524

申请日：2012-10-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L29/92

CPC classification number: H01L28/40 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02356 ,  H01L27/10852 ,  H01L28/75

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 金属氧化物第二电极层形成在电介质层的上方。 金属氧化物第二电极层具有与电介质层的晶体结构相容的晶体结构。 可选地，在金属氧化物第二电极层上形成第二电极体层。

公开(公告)号：US20130095632A1

公开(公告)日：2013-04-18

申请号：US13708035

申请日：2012-12-07

Applicant: Intermolecular, Inc.

Inventor： Xiangxin Rui ,  Hanhong Chen ,  Pragati Kumar ,  Sandra G. Malhotra

IPC: H01L21/02

CPC classification number: H01L21/02 ,  B82Y99/00 ,  C01G23/047 ,  C01P2002/72 ,  C23C16/0272 ,  C23C16/34 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02186 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

公开(公告)号：US20130093051A1

公开(公告)日：2013-04-18

申请号：US13692460

申请日：2012-12-03

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Hanhong Chen ,  Hiroyuki Ode

IPC: H01L49/02

CPC classification number: H01L28/65 ,  H01L27/10805 ,  H01L28/75

Abstract: A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO2 and RuO2. The capacitor stack including the bottom layer is subjected to a PMA treatment to reduce the oxygen vacancies in the dielectric layer and reduce the interface states at the dielectric/second electrode interface. The other component of the bilayer (i.e. top layer) is a high work function, high conductivity metal or conductive metal compound.

Abstract translation: 形成用于MIM DRAM电容器的双层第二电极，其中与电介质层（即底层）接触的电极层具有在随后的退火步骤期间耐氧化的组成并具有金红石模板能力。 实例包括SnO 2和RuO 2。 包括底层的电容器堆叠经受PMA处理以减少电介质层中的氧空位并降低电介质/第二电极界面处的界面态。 双层的另一组分（即顶层）是高功函数，高导电性金属或导电金属化合物。