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    Doped electrodes for DRAM applications
    21.
    发明授权
    Doped electrodes for DRAM applications 有权
    用于DRAM应用的掺杂电极

    公开(公告)号：US08569819B1

    公开(公告)日：2013-10-29

    申请号：US13915050

    申请日：2013-06-11

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

    Inventor： Xiangxin Rui ,  Hiroyuki Ode

    IPC: H01L27/108 ,  H01L29/94 ,  H01L21/8242 ,  H01L21/329

    CPC classification number: H01L28/65 ,  H01L28/40 ,  H01L28/60

    Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 μΩcm. Advantageously, the electrode layers are conductive molybdenum oxide.

    Abstract translation: 形成用于MIM DRAM电容器的金属氧化物第一电极层，其中第一和/或第二电极层含有一个或多个掺杂剂，直到总掺杂浓度，其将不会阻止电极层在随后的退火步骤期间结晶。 一种或多种掺杂剂具有大于约5.0eV的功函数。 一种或多种掺杂剂的电阻率小于约1000μOggacm。 有利地，电极层是导电性氧化钼。

    Blocking layers for leakage current reduction in DRAM devices
    22.
    发明授权
    Blocking layers for leakage current reduction in DRAM devices 有权

    公开(公告)号：US08569818B2

    公开(公告)日：2013-10-29

    申请号：US13658065

    申请日：2012-10-23

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L29/94 ,  H01L21/20

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    High performance dielectric stack for DRAM capacitor
    23.
    发明授权
    High performance dielectric stack for DRAM capacitor 有权
    用于DRAM电容器的高性能电介质堆叠

    公开(公告)号：US08546236B2

    公开(公告)日：2013-10-01

    申请号：US13738866

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L21/20 ,  H01L21/31

    CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

    Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

    Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

    Blocking Layers for Leakage Current Reduction in DRAM Devices
    26.
    发明申请
    Blocking Layers for Leakage Current Reduction in DRAM Devices 有权
    阻止DRAM器件泄漏电流降低的层

    公开(公告)号：US20130113079A1

    公开(公告)日：2013-05-09

    申请号：US13658065

    申请日：2012-10-23

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L29/92

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

    High Temperature ALD Process for Metal Oxide for DRAM Applications
    28.
    发明申请
    High Temperature ALD Process for Metal Oxide for DRAM Applications 有权
    金属氧化物用于DRAM应用的高温ALD工艺

    公开(公告)号：US20140077337A1

    公开(公告)日：2014-03-20

    申请号：US13737156

    申请日：2013-01-09

    Applicant: INTERMOLECULAR, INC.

    Inventor： Hanhong Chen ,  Edward Haywood ,  Sandra Malhotra ,  Hiroyuki Ode

    IPC: H01L29/92

    CPC classification number: H01L29/92 ,  C23C16/45525 ,  H01L21/28562 ,  H01L28/65 ,  H01L28/75

    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive metal oxide formed using a high temperature, low pressure ALD process. The high temperature ALD process results in a layer with enhanced crystallinity, higher density, reduced shrinkage, and lower carbon contamination. The high temperature ALD process can be used for either or both the bottom electrode and the top electrode layers.

    Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层含有使用高温低压ALD工艺形成的导电金属氧化物。 高温ALD工艺产生了具有增强的结晶度，较高密度，降低的收缩率和较低的碳污染的层。 高温ALD工艺可以用于底部电极和顶部电极层中的一个或两个。

    Manufacturable High-k dram mim capacitor structure
    29.
    发明申请
    Manufacturable High-k dram mim capacitor structure 有权
    可制造的高电容电容器结构

    公开(公告)号：US20130328168A1

    公开(公告)日：2013-12-12

    申请号：US13737467

    申请日：2013-01-09

    Applicant: INTERMOLECULAR INC.

    Inventor： Sandra G. Malhotra ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L49/02

    CPC classification number: H01L28/56 ,  H01L27/10852 ,  H01L28/60 ,  H01L28/90

    Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.

    Abstract translation: 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电介质材料形成在第一电极材料之上。 第一电极材料是刚性的并且具有良好的机械强度并且用作用于电容器叠层的坚固框架。 第一介电材料足够薄（<2nm）或高度掺杂，使得在随后的退火处理之后它保持非晶态。 在第一电介质材料上方形成第二电介质材料。 第二介电材料足够厚（> 3nm）或轻掺杂或未掺杂，使得其在随后的退火处理之后结晶。 与第二电介质材料相邻地形成第二电极材料。 第二电极材料具有高功函数和用于促进形成第二电介质材料的高k值晶体结构的晶体结构。

    Enhanced non-noble electrode layers for DRAM capacitor cell
    30.
    发明授权
    Enhanced non-noble electrode layers for DRAM capacitor cell 有权
    用于DRAM电容器电池的增强型非贵金属电极层

    公开(公告)号：US08581318B1

    公开(公告)日：2013-11-12

    申请号：US13737209

    申请日：2013-01-09

    Applicant: Intermolecular, Inc.

    Inventor： Hanhong Chen ,  Wim Deweerd ,  Edward L. Haywood ,  Sandra G. Malhotra ,  Hiroyuki Ode

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L28/60 ,  H01L28/75

    Abstract: A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩcm. Advantageously, the electrode materials are conductive molybdenum oxide.

    Abstract translation: 形成用于MIM DRAM电容器的金属氧化物第一电极材料，其中第一和/或第二电极材料或结构包含具有一个或多个掺杂剂的层，直到总掺杂浓度，其将不会阻止电极材料在随后的退火期间结晶 步。 有利地，掺杂有一种或多种掺杂剂的电极具有大于约5.0eV的功函数。 有利地，掺杂有一种或多种掺杂剂的电极具有小于约1000微米的电阻率。 有利地，电极材料是导电性氧化钼。

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