公开(公告)号：US20130140619A1

公开(公告)日：2013-06-06

申请号：US13738866

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Sandra Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

公开(公告)号：US20130095632A1

公开(公告)日：2013-04-18

申请号：US13708035

申请日：2012-12-07

Applicant: Intermolecular, Inc.

Inventor： Xiangxin Rui ,  Hanhong Chen ,  Pragati Kumar ,  Sandra G. Malhotra

IPC: H01L21/02

CPC classification number: H01L21/02 ,  B82Y99/00 ,  C01G23/047 ,  C01P2002/72 ,  C23C16/0272 ,  C23C16/34 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02186 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

公开(公告)号：US20130072015A1

公开(公告)日：2013-03-21

申请号：US13675852

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati Kumar ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L21/285

CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

公开(公告)号：US20130059066A1

公开(公告)日：2013-03-07

申请号：US13658595

申请日：2012-10-23

Applicant: Intermolecular, Inc

Inventor： Xiangxin Rui ,  Iain Buchanan ,  Moo-Sung Kim ,  Xinjian Lei ,  Laura Matz ,  Sunil Shanker

IPC: B05D5/12

CPC classification number: C23C16/45531 ,  C23C16/409 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/3142 ,  H01L21/31691 ,  H01L28/56

Abstract: Embodiments of the current invention include methods of forming a strontium titanate (SrTiO3) film using atomic layer deposition (ALD). More particularly, the method includes forming a plurality of titanium oxide (TiO2) unit films using ALD and forming a plurality of strontium oxide (SrO) unit films using ALD. The combined thickness of the TiO2 and SrO unit films is less than approximately 5 angstroms. The TiO2 and SrO units films are then annealed to form a strontium titanate layer.

Abstract translation: 本发明的实施方案包括使用原子层沉积（ALD）形成钛酸锶（SrTiO 3）膜的方法。 更具体地说，该方法包括使用ALD形成多个氧化钛（TiO 2）单元膜并使用ALD形成多个氧化锶（SrO）单元膜。 TiO 2和SrO单元膜的组合厚度小于约5埃。 然后将TiO 2和SrO单元膜退火以形成钛酸锶层。

公开(公告)号：US20130056852A1

公开(公告)日：2013-03-07

申请号：US13668488

申请日：2012-11-05

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Edward L. Haywood ,  Sandra G. Malhotra ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L29/92

CPC classification number: H01L21/3141 ,  C23C16/02 ,  C23C16/405 ,  H01L21/02186 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31604 ,  H01L28/91

Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.

Abstract translation: 描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角 并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种在暴露的金属上沉积氧化钛层，其中所述氧化钛层包含至少一部分金红石型氧化钛。

公开(公告)号：US08975147B2

公开(公告)日：2015-03-10

申请号：US13708035

申请日：2012-12-07

Applicant: Intermolecular, Inc.

Inventor： Xiangxin Rui ,  Hanhong Chen ,  Pragati Kumar ,  Sandra G. Malhotra

IPC: H01L21/02 ,  C01G23/047 ,  C23C16/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  H01L49/02 ,  H01L27/108 ,  B82Y99/00

CPC classification number: H01L21/02 ,  B82Y99/00 ,  C01G23/047 ,  C01P2002/72 ,  C23C16/0272 ,  C23C16/34 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02186 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

Abstract translation: 本公开提供了制造半导体堆叠和相关设备（诸如电容器和DRAM单元）的方法。 特别地，底部电极具有选择用于晶格匹配特性的材料。 该材料可以由相对廉价的金属氧化物制成，其被处理成具有特定结晶形式的导电但难以产生的氧化物状态; 为了提供一个实例，公开了与用作电介质的金红石相二氧化钛（TiO 2）的生长相容的具体材料，从而导致可预测和可再现的较高介电常数和较低的有效氧化物厚度，因此更大的部分密度 以较低的成本。

公开(公告)号：US08581319B2

公开(公告)日：2013-11-12

申请号：US13738901

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L29/94

CPC classification number: H01L28/56 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02304 ,  H01L28/40

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.

Abstract translation: 一种用于制造动态随机存取存储器（DRAM）电容器的方法包括：形成第一电极层，在第一电极层上形成催化层，任选地退火催化层，在催化层上形成电介质层， 在电介质层上形成第二电极层，并且可选地对电容器堆叠进行退火。 有利地，电极层是TiN，催化剂层是MoO 2-x，其中x在0和2之间，催化层的物理厚度在约0.5nm和约10nm之间，并且电介质层是ZrO 2。

公开(公告)号：US09082782B2

公开(公告)日：2015-07-14

申请号：US13655653

申请日：2012-10-19

Applicant: Intermolecular Inc.

Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati Kumar ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L29/02 ,  H01L49/02 ,  C23C16/40 ,  H01L27/108

CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.

公开(公告)号：US20130140675A1

公开(公告)日：2013-06-06

申请号：US13738901

申请日：2013-01-10

Applicant: Intermolecular, Inc.

Inventor： Hanhong Chen ,  Sandra Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC: H01L49/02

CPC classification number: H01L28/56 ,  H01L21/02175 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/02304 ,  H01L28/40

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2−x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.

Abstract translation: 一种用于制造动态随机存取存储器（DRAM）电容器的方法包括：形成第一电极层，在第一电极层上形成催化层，任选地退火催化层，在催化层上形成电介质层， 在电介质层上形成第二电极层，并且可选地对电容器堆叠进行退火。 有利地，电极层是TiN，催化剂层是MoO 2-x，其中x在0和2之间，催化层的物理厚度在约0.5nm和约10nm之间，并且电介质层是ZrO 2。

公开(公告)号：US20130037913A1

公开(公告)日：2013-02-14

申请号：US13655653

申请日：2012-10-19

Applicant: INTERMOLECULAR INC.

Inventor： Hanhong Chen ,  Toshiyuki Hirota ,  Pragati KUMAR ,  Xiangxin Rui ,  Sunil Shanker

IPC: H01L29/02

CPC classification number: H01L28/60 ,  C23C16/405 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.