公开(公告)号：US20230165170A1

公开(公告)日：2023-05-25

申请号：US17531149

申请日：2021-11-19

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  JUNTAO LI ,  ZUOGUANG LIU ,  Arthur Gasasira

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/24 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1608

Abstract: A phase change memory includes a substrate, a plurality of first phase change elements on the substrate, a plurality of electrodes on the plurality of first phase change elements, and a second phase change element connecting the plurality of electrodes and disposed between the plurality of first phase change elements.

公开(公告)号：US20230079751A1

公开(公告)日：2023-03-16

申请号：US17472759

申请日：2021-09-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kangguo Cheng ,  JUNTAO LI ,  Carl Radens

IPC: H01L27/092 ,  H01L21/8238

Abstract: An approach provides a semiconductor structure for a first device with a first plurality of channels with a larger horizontal dimension than a vertical dimension of the first plurality of channels a second device comprising a second plurality of channels with a smaller horizontal dimension than the vertical dimension of the second plurality of channels. The first plurality of channels and the second plurality of channels have a same channel width in embodiments of the present invention. The first device is an n-type horizontal gate-all-around device and the second device is a p-type horizontal gate-all-around device.

公开(公告)号：US20220285614A1

公开(公告)日：2022-09-08

申请号：US17192223

申请日：2021-03-04

Applicant: International Business Machines Corporation

Inventor： JUNTAO LI ,  Kangguo Cheng ,  DEXIN KONG ,  ZHENG XU

IPC: H01L45/00 ,  H01L27/24

Abstract: An approach to form a semiconductor structure with a multiple layer phase change material stack and four electrodes that functions as an integrated switch device. The semiconductor structure includes a sidewall spacer that is on two opposing sides of the multiple layer phase change material stack contacting an edge of each layer of the multiple layer phase change material stack. The semiconductor structure includes a pair of a first type of electrode, where each of the pair of the first type of electrode abuts each of the sidewall spacers on the two opposing sides of the multiple layer phase change material stack. A pair of a second type of electrode, where each of the second type of electrode abuts each of two other opposing sides of the multiple layer phase change material stack and contacts a heater material on outside portions of the multiple layer phase change material stack.

公开(公告)号：US20210159405A1

公开(公告)日：2021-05-27

申请号：US16691646

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Carl Radens ,  Kangguo Cheng ,  JUNTAO LI ,  Ruilong Xie

IPC: H01L45/00

Abstract: A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening.

公开(公告)号：US20200091288A1

公开(公告)日：2020-03-19

申请号：US16134203

申请日：2018-09-18

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  JUNTAO LI ,  Shogo Mochizuki

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L21/56 ,  H01L21/8238

Abstract: A nanosheet field effect transistor device includes a semiconductor substrate including a stack of semiconductor nanosheets and a gate structure. The gate structure has an electrically conductive gate contact on the nanosheets and defines a channel region interposed between opposing source or drain (S/D) regions. The nanosheet field effect transistor further includes an electrically conductive cladding layer that encapsulates an outer surface of the S/D regions, and inner spacers on the sidewalls of the gate structure. The inner spacers are interposed between the cladding layer and the gate contact.

公开(公告)号：US20200051850A1

公开(公告)日：2020-02-13

申请号：US16598458

申请日：2019-10-10

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  EKMINI A. DE SILVA ,  JUNTAO LI ,  YI SONG ,  PENG XU

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/762

Abstract: A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation.

公开(公告)号：US20180090605A1

公开(公告)日：2018-03-29

申请号：US15607796

申请日：2017-05-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  GENG WANG ,  QINTAO ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.

公开(公告)号：US20180053758A1

公开(公告)日：2018-02-22

申请号：US15698041

申请日：2017-09-07

Applicant: International Business Machines Corporation

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  GENG WANG ,  QINTAO ZHANG

IPC: H01L27/06 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/868 ,  H01L29/78 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0255 ,  H01L27/092 ,  H01L29/0657 ,  H01L29/66136 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/868

Abstract: An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.

公开(公告)号：US20230154925A1

公开(公告)日：2023-05-18

申请号：US17528391

申请日：2021-11-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Julien Frougier ,  Ruilong Xie ,  JUNTAO LI

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A semiconductor FET (field effect transistor) including a plurality of nanosheet channels disposed between a first source/drain region and a second source/drain region and a common metal contact for the first source/drain region and the second source/drain region. The first source/drain region includes a p-type material; and the second source/drain region includes an n-type material.

公开(公告)号：US20230086888A1

公开(公告)日：2023-03-23

申请号：US17482573

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  SHOGO MOCHIZUKI ,  JUNTAO LI

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12

Abstract: A dielectric layer is on top of a first semiconductor stack. The first semiconductor stack is compressively strained. A second semiconductor stack is on top of the dielectric layer. The second semiconductor stack is tensely strained.