公开(公告)号：US10824508B2

公开(公告)日：2020-11-03

申请号：US16386577

申请日：2019-04-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Patrick J. Meaney ,  Christian Jacobi ,  Barry M. Trager

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  H03M13/09 ,  G11C29/04

Abstract: A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols for the memory modules. A host receives and decodes the ECC symbols and executes error correction operations. The host and the memory modules are coupled by a number of channels.

公开(公告)号：US10666540B2

公开(公告)日：2020-05-26

申请号：US15651346

申请日：2017-07-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Luiz C. Alves ,  Patrick J. Meaney ,  Christopher N. Oelsner ,  Gary A. Peterson ,  Christopher Steffen

IPC: H04L1/00 ,  H04L12/26 ,  H04L12/24 ,  G06F13/40 ,  G06F13/42

Abstract: A technique relates to dynamic time-domain reflectometry (TDR). A machine spares a bad lane in a bus. The bad lane is taken offline. TDR is dynamically executed on the bad lane while the bus is still in operation. A defect is isolated using results of the TDR.

公开(公告)号：US20190317856A1

公开(公告)日：2019-10-17

申请号：US15953805

申请日：2018-04-16

Applicant: International Business Machines Corporation

Inventor： James A. O'Connor, JR. ,  Barry M. Trager ,  Warren E. Maule ,  Marc A. Gollub ,  Brad W. Michael ,  Patrick J. Meaney

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

公开(公告)号：US20190252010A1

公开(公告)日：2019-08-15

申请号：US16397154

申请日：2019-04-29

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Susan M. Eickhoff ,  Warren E. Maule ,  Patrick J. Meaney ,  Stephen J. Powell ,  Gary A. Van Huben ,  Jie Zheng

IPC: G11C7/10 ,  G06F3/06

CPC classification number: G11C7/109 ,  G06F3/0611 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/08 ,  G11C5/04 ,  G11C7/1003 ,  G11C7/1078 ,  G11C7/22 ,  G11C2207/2245

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

公开(公告)号：US20190227741A1

公开(公告)日：2019-07-25

申请号：US15877661

申请日：2018-01-23

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Markus Cebulla ,  Susan M. Eickhoff ,  Logan I. Friedman ,  Patrick J. Meaney ,  Walter Pietschmann ,  Nicholas Rolfe ,  Gary A. Van Huben

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.

公开(公告)号：US10353606B2

公开(公告)日：2019-07-16

申请号：US15782089

申请日：2017-10-12

Applicant: International Business Machines Corporation

Inventor： Susan M. Eickhoff ,  Steven R. Carlough ,  Patrick J. Meaney ,  Stephen J. Powell ,  Jie Zheng ,  Gary A. Van Huben

IPC: G06F3/06

Abstract: A host divides a dataset into stripes and sends the stripes to respective data chips of a distributed memory buffer system, where the data chips buffer the respective slices. Each data chip can buffer stripes from multiple datasets. Through the use of: (i) error detection methods; (ii) tagging the stripes for identification; and (iii) acknowledgement responses from the data chips, the host keeps track of the status of each slice at the data chips. If errors are detected for a given stripe, the host resends the stripe in the next store cycle, concurrently with stripes for the next dataset. Once all stripes have been received error-free across all the data chips, the host issues a store command which triggers the data chips to move the respective stripes from buffer to memory.

公开(公告)号：US20190158218A1

公开(公告)日：2019-05-23

申请号：US15817408

申请日：2017-11-20

Applicant: International Business Machines Corporation

Inventor： Steven R. Carlough ,  Patrick J. Meaney ,  Gary Van Huben

IPC: H04L1/00 ,  H04L1/20

Abstract: Aspects of the invention include receiving a specified number of frames of bits at a receiver. At least one of the received frames includes cyclic redundancy code (CRC) bits. The specified number of frames is based at least in part on a CRC rate. It is determined, by performing a CRC check on the received frames, whether a change in transmission errors has occurred in the received frames. An increase in the CRC rate is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred in the received frames. The increase in the CRC rate is synchronized between the receiver and the transmitter; and performed in parallel with functional operations performed by the receiver.

公开(公告)号：US20180365177A1

公开(公告)日：2018-12-20

申请号：US15623960

申请日：2017-06-15

Applicant: International Business Machines Corporation

Inventor： David D. Cadigan ,  Thomas J. Dewkett ,  Glenn D. Gilda ,  Patrick J. Meaney ,  Craig R. Walters

IPC: G06F13/16

CPC classification number: G06F13/1684 ,  G06F13/1647

Abstract: A processor implemented method for spreading data traffic across memory controllers with respect to conditions is provided. The processor implemented method includes determining whether the memory controllers are balanced. The processor implemented method includes executing a conditional spreading with respect to the conditions when the memory controllers are determined as unbalanced. The processor implemented method includes executing an equal spreading when the memory controllers are determined as balanced.

公开(公告)号：US09946595B2

公开(公告)日：2018-04-17

申请号：US14870347

申请日：2015-09-30

Applicant: International Business Machines Corporation

Inventor： Glenn D. Gilda ,  Patrick J. Meaney

IPC: H03M13/05 ,  G06F11/10 ,  G11C29/52 ,  G11C29/44

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C29/44 ,  G11C29/52

Abstract: In some embodiments, a computer-implemented method includes maintaining two or more error indicators for correctable errors occurring at two or more memory components. Each of the error indicators may be associated with a corresponding memory component. A correctable error may be detected as occurring during a first memory fetch operation at a first memory component. A first error indicator corresponding to the first memory component may be set, responsive to the correctable error at the first memory component. An uncorrectable error may be detected during a second memory fetch operation. It may be detected that the first error indicator is set. The first memory component may be marked, responsive to the uncorrectable error and to detecting that the first error indicator is set. The two or more error indicators for correctable errors may thus determine which memory component to mark due to the uncorrectable error.

公开(公告)号：US20170193232A1

公开(公告)日：2017-07-06

申请号：US14987002

申请日：2016-01-04

Applicant: International Business Machines Corporation

Inventor： Ralph A. Rabasco ,  John P. Mullin ,  Neil A. Trapani ,  Patrick J. Meaney

IPC: G06F21/60 ,  G06F3/06

CPC classification number: G06F21/60 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/067 ,  G06F3/0689 ,  G06F21/78 ,  G06F2221/2143

Abstract: A method for securely removing data from a storage system is disclosed. In one embodiment, such a method includes receiving, by a storage system, instructions to erase logical units from the storage system. In response to receiving the instructions, the storage system maps the logical units to physical extents on the storage system. The storage system then initiates, using at least one of hardware and software embedded in the storage system, a secure data removal process that securely erases data from the physical extents by overwriting the data thereon, while leaving intact data stored on other physical extents of the storage system. The storage system is configured to process I/O to the other physical extents during execution of the secure data removal process. A corresponding system and computer program product are also disclosed.