公开(公告)号：US20130230949A1

公开(公告)日：2013-09-05

申请号：US13845506

申请日：2013-03-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

Abstract translation: 填充深沟槽的节点电介质和导电沟槽填充区域凹陷到与绝缘体上半导体（SOI）层的顶表面基本上共面的深度。 浅沟槽隔离部分形成在深沟槽的上部的一侧上，而深沟槽的上部的另一侧提供导电填充区域的半导体材料的暴露表面。 执行选择性外延工艺以沉积升高的源极区域和升高的带状区域。 升高的源极区域直接形成在SOI层内的平坦的源极区域上，并且凸起的带区域直接形成在导电填充区域上。 升高的带区域接触升高的源极区域，以在平面源极区域和导电填充区域之间提供导电路径。

公开(公告)号：US09397152B2

公开(公告)日：2016-07-19

申请号：US14851345

申请日：2015-09-11

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L21/8242 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L21/32134 ,  H01L28/86 ,  H01L28/90 ,  H01L28/91

Abstract: A semiconductor capacitor and method of fabrication is disclosed. A MIM stack, having alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

Abstract translation: 公开了一种半导体电容器及其制造方法。 在深空腔中形成具有交替的第一和第二类金属层（各自被电介质隔离）的MIM堆叠。 整个堆叠可以被平坦化，然后被图案化以暴露第一区域，并且被选择性地蚀刻以在第一区域内凹陷所有第一金属层。 执行第二选择性蚀刻以在第二区域内凹陷所有第二金属层。 蚀刻的凹槽可以用电介质回填。 可以形成单独的电极; 第一电极，形成在所述第一区域中，并且与所有所述第二类型金属层和所述第一类型金属层接触，并且形成在所述第二区域中并与所有第一类金属层接触的第二电极， 所述第二类金属层。

公开(公告)号：US20150287721A1

公开(公告)日：2015-10-08

申请号：US14746017

申请日：2015-06-22

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

Abstract translation: 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

公开(公告)号：US20140120688A1

公开(公告)日：2014-05-01

申请号：US14146198

申请日：2014-01-02

Applicant: International Business Machines Corporation

Inventor： Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L27/1203 ,  H01L29/945

Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

Abstract translation: 在绝缘体上半导体（SOI）衬底中形成具有不同宽度的两个沟槽。 在沟槽中形成不透氧层和填充材料层。 从第一沟槽内去除填充材料层和不透氧层。 执行热氧化以将第一沟槽的侧壁下方的半导体材料转换成上部热氧化物部分和下部热氧化物部分，而在第二沟槽的侧壁上的剩余的不透氧层防止半导体材料的氧化。 在第二沟槽的侧壁上形成节点电介质之后，沉积导电材料以填充沟槽，从而分别形成导电沟槽填充部分和内部电极。 上部和下部热氧化物部分用作电绝缘两个器件区域的介电材料部分的部件。

公开(公告)号：US09899391B2

公开(公告)日：2018-02-20

申请号：US15400055

申请日：2017-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

公开(公告)号：US09287272B2

公开(公告)日：2016-03-15

申请号：US14467580

申请日：2014-08-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/66 ,  H01L21/74 ,  H01L21/762 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L27/10829 ,  H01L21/743 ,  H01L21/76283 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/60 ,  H01L28/92 ,  H01L29/0649 ,  H01L29/66181

Abstract: A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Abstract translation: 提供了高k电介质金属沟槽电容器和改进的隔离及其制造方法。 该方法包括在衬底中形成至少一个深沟槽，并用牺牲填充材料和聚合材料填充深沟槽。 该方法还包括继续CMOS工艺，包括形成至少一个晶体管和后端（BEOL）层。 该方法还包括从深沟槽去除牺牲填充材料以暴露侧壁，以及在深沟槽的暴露的侧壁上形成电容器板。 该方法还包括用高k电介质材料衬套电容器板，并用金属材料在高k电介质材料上填充深沟槽的剩余部分。 该方法还包括在填充有金属材料和高k电介质材料的深沟槽上提供钝化层。

公开(公告)号：US09257433B2

公开(公告)日：2016-02-09

申请号：US14736695

申请日：2015-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

公开(公告)号：US09224801B2

公开(公告)日：2015-12-29

申请号：US14532281

申请日：2014-11-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/3213

CPC classification number: H01L28/40 ,  H01L21/32134 ,  H01L28/86 ,  H01L28/90 ,  H01L28/91

Abstract: An improved semiconductor capacitor and method of fabrication is disclosed. A MIM stack, comprising alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

公开(公告)号：US09159578B2

公开(公告)日：2015-10-13

申请号：US14188814

申请日：2014-02-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L21/302 ,  B44C1/22 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

Abstract: A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the patterned line to the substrate.

Abstract translation: 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和图案化线的图案转移到衬底。

公开(公告)号：US09059213B2

公开(公告)日：2015-06-16

申请号：US13845506

申请日：2013-03-18

Applicant: International Business Machines Corporation

Inventor： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ali Khakifirooz ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L21/8242 ,  H01L27/12 ,  H01L29/94 ,  H01L29/66 ,  H01L27/108 ,  H01L21/84

CPC classification number: H01L29/66742 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: A node dielectric and a conductive trench fill region filling a deep trench are recessed to a depth that is substantially coplanar with a top surface of a semiconductor-on-insulator (SOI) layer. A shallow trench isolation portion is formed on one side of an upper portion of the deep trench, while the other side of the upper portion of the deep trench provides an exposed surface of a semiconductor material of the conductive fill region. A selective epitaxy process is performed to deposit a raised source region and a raised strap region. The raised source region is formed directly on a planar source region within the SOI layer, and the raised strap region is formed directly on the conductive fill region. The raised strap region contacts the raised source region to provide an electrically conductive path between the planar source region and the conductive fill region.

Abstract translation: 填充深沟槽的节点电介质和导电沟槽填充区域凹陷到与绝缘体上半导体（SOI）层的顶表面基本上共面的深度。 浅沟槽隔离部分形成在深沟槽的上部的一侧上，而深沟槽的上部的另一侧提供导电填充区域的半导体材料的暴露表面。 执行选择性外延工艺以沉积升高的源极区域和升高的带状区域。 升高的源极区域直接形成在SOI层内的平坦的源极区域上，并且凸起的带区域直接形成在导电填充区域上。 升高的带区域接触升高的源极区域，以在平面源极区域和导电填充区域之间提供导电路径。