公开(公告)号：US20130217219A1

公开(公告)日：2013-08-22

申请号：US13842217

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

Abstract translation: 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

公开(公告)号：US12068415B2

公开(公告)日：2024-08-20

申请号：US17966817

申请日：2022-10-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78642 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US11990412B2

公开(公告)日：2024-05-21

申请号：US17488389

申请日：2021-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Stuart Sieg ,  Somnath Ghosh ,  Kisik Choi ,  Rishikesh Krishnan ,  Alexander Reznicek

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L23/5286 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392

Abstract: Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

公开(公告)号：US20230029561A1

公开(公告)日：2023-02-02

申请号：US17966817

申请日：2022-10-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US20210391473A1

公开(公告)日：2021-12-16

申请号：US16901852

申请日：2020-06-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US09299766B2

公开(公告)日：2016-03-29

申请号：US14242092

申请日：2014-04-01

Applicant: International Business Machines Corporation

Inventor： Nicolas L. Breil ,  Ricardo A. Donaton ,  Dong Hun Kang ,  Herbert L. Ho ,  Rishikesh Krishnan

IPC: H01L21/20 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L21/283 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/1087 ,  H01L28/90

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench; epitaxially forming a compressive stress layer in the lower portion of the deep trench; forming a metal-insulator-metal (MIM) stack within the lower portion of the deep trench; and filling a remaining portion of the deep trench with a semiconductor. Alternatively to forming the compressive stress layer or in addition thereto, a silicide may be formed by co-deposition of a refractory metal and silicon.

Abstract translation: 提供形成深沟槽电容器的方法。 该方法可以包括在衬底中形成深沟槽; 将所述深沟槽的下部的宽度扩大为比所述深沟槽的其余部分的宽度宽; 在深沟槽的下部外延形成压应力层; 在深沟槽的下部形成金属 - 绝缘体 - 金属（MIM）堆叠; 以及用半导体填充深沟槽的剩余部分。 除了形成压应力层之外，或者除此之外，还可以通过共沉积难熔金属和硅来形成硅化物。

公开(公告)号：US09099394B2

公开(公告)日：2015-08-04

申请号：US14066119

申请日：2013-10-29

Applicant: International Business Machines Corporation

Inventor： Nicolas Breil ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon

IPC: H01L27/112 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L27/115 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49

CPC classification number: H01L21/28273 ,  H01L21/0228 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/11546 ,  H01L29/42376 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7881

Abstract: A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.

Abstract translation: 在半导体衬底上同时形成用于场效应晶体管（FET）的高介电常数（高k）栅极电介质和非易失性随机存取存储器（NVRAM）器件的高k隧道电介质。 随后沉积至少一个导电材料层，控制栅极电介质层和一次性材料层的堆叠并且被光刻图案化。 沉积并图案化平坦化介电层，并且去除一次性材料部分。 控制栅极电介质层的剩余部分保留在NVRAM器件区域中，但在FET区域中被去除。 导电材料沉积在栅极腔中以为NVRAM器件提供控制栅极和用于FET的栅极部分。 或者，控制栅介质层可以用NVRAM器件区域中的高k控制栅极电介质代替。

公开(公告)号：US11515427B2

公开(公告)日：2022-11-29

申请号：US16901852

申请日：2020-06-15

Applicant: International Business Machines Corporation

Inventor： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08

Abstract: Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

公开(公告)号：US20220069104A1

公开(公告)日：2022-03-03

申请号：US17521964

申请日：2021-11-09

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US11081583B2

公开(公告)日：2021-08-03

申请号：US16665338

申请日：2019-10-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Keith H. Tabakman ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

Abstract: A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.