公开(公告)号：US08959289B2

公开(公告)日：2015-02-17

申请号：US13655699

申请日：2012-10-19

Applicant: International Business Machines Corporation

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  William J. Starke ,  Jeff A. Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0897 ,  G06F12/126

Abstract: A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.

Abstract translation: 数据处理系统包括由上层和下层高速缓存支持的处理器核心。 响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。 响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。 为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存 线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。

公开(公告)号：US20140165056A1

公开(公告)日：2014-06-12

申请号：US13711004

申请日：2012-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Geraint North ,  William J. Starke ,  Phillip G. Williams

IPC: G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F11/00 ,  G06F11/1484 ,  G06F11/202 ,  G06F11/2041 ,  G06F11/2097 ,  G06F12/0891 ,  G06F2009/45583

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache comprising a plurality of cache rows (1210), each cache row comprising a cache line (1214) and an image modification flag (1217) indicating a modification of said cache line caused by the running of the virtual machine; and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit comprises a replication manager adapted to define a log (200) in the memory prior to running the virtual machine in said first operating mode; and said cache further includes a cache controller (122) adapted to periodically check said image modification flags; write only the memory address of the flagged cache lines in the defined log and subsequently clear the image modification flags. A computer cluster including such computer systems and a method of managing such a computer cluster are also disclosed.

Abstract translation: 公开了一种包括适于以第一操作模式运行虚拟机的处理器单元（110）的计算机系统（100） 所述高速缓存包括多个高速缓存行（1210），每个高速缓存行包括高速缓存行（1214）和指示所述高速缓存行的修改的图像修改标志（1217），所述高速缓存行指示由 虚拟机的运行; 以及高速缓存控制器可访问的存储器（140），用于存储所述虚拟机的图像; 其中所述处理器单元包括适于在所述第一操作模式中运行所述虚拟机之前在所述存储器中定义日志（200）的复制管理器; 并且所述高速缓存还包括适于周期性地检查所述图像修改标志的高速缓存控制器（122） 只写入定义的日志中标记的高速缓存行的存储器地址，然后清除映像修改标志。 还公开了包括这种计算机系统的计算机集群和管理这种计算机集群的方法。

公开(公告)号：US11947461B2

公开(公告)日：2024-04-02

申请号：US17572245

申请日：2022-01-10

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Naga P. Gorti ,  Guy L. Guthrie ,  Sanjeev Ghai

IPC: G06F12/0862 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0871

CPC classification number: G06F12/0862 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0871 ,  G06F2212/1021

Abstract: A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.

公开(公告)号：US11157411B2

公开(公告)日：2021-10-26

申请号：US16691776

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Stephen J. Powell ,  William J. Starke

IPC: G06F12/08 ,  G06F12/0855 ,  G06F12/126

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

公开(公告)号：US11106608B1

公开(公告)日：2021-08-31

申请号：US16908272

申请日：2020-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Sanjeev Ghai

IPC: G06F12/14 ,  G06F16/11 ,  G06F13/16 ,  G06F9/30 ,  G06F13/40 ,  G06F30/32 ,  G06F115/10

Abstract: A processing unit includes a processor core that executes a store-conditional instruction that generates a store-conditional request specifying a store target address. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The cache includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request snooped on a system interconnect during a protection window extension following servicing of the store-conditional request. The cache is configured to vary a duration of the protection window extension for different snooped memory access requests based on one of broadcast scopes and the relative locations of masters of the snooped memory access requests.

公开(公告)号：US09792208B2

公开(公告)日：2017-10-17

申请号：US14170172

申请日：2014-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/00 ,  G06F12/0804 ,  G06F11/14 ,  G06F12/0811 ,  G06F11/20

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0811

Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

公开(公告)号：US09390024B2

公开(公告)日：2016-07-12

申请号：US14311447

申请日：2014-06-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy L Guthrie ,  Hugh Shen ,  Derek E. Williams

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F13/00 ,  G06F13/28 ,  G06F9/38

CPC classification number: G06F12/0888 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0833 ,  G06F12/0895 ,  G06F12/128

Abstract: In response to receipt of a store-conditional (STCX) request of a processor core, the STCX request is buffered in an entry of a store queue for eventual service by a read-claim (RC) machine by reference to a cache array, and the STCX request is concurrently transmitted via a bypass path bypassing the store queue. In response to dispatch logic dispatching the STCX request transmitted via the bypass path to the RC machine for service by reference to the cache array, the entry of the STCX request in the store queue is updated to prohibit selection of the STCX request in the store queue for service. In response to the STCX request transmitted via the bypass path not being dispatched by the dispatch logic, the STCX is thereafter transmitted from the store queue to the dispatch logic and dispatched to the RC machine for service by reference to the cache array.

Abstract translation: 响应于接收到处理器核心的存储条件（STCX）请求，STCX请求被缓存在存储队列的条目中，以通过参考高速缓存阵列由读取（RC）机器最终服务，并且 通过旁路存储队列的旁路路径同时发送STCX请求。 响应于调度逻辑将通过旁路路径发送的STCX请求通过参考高速缓存阵列发送到RC机器进行服务，更新存储队列中的STCX请求的条目，以禁止在存储队列中选择STCX请求 服务。 响应于通过不由调度逻辑分派的旁路路径发送的STCX请求，STCX此后从存储队列发送到调度逻辑，并通过参考高速缓存阵列发送到RC机进行服务。

公开(公告)号：US09336142B2

公开(公告)日：2016-05-10

申请号：US14073531

申请日：2013-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/00 ,  G06F12/08 ,  G06F11/14

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0811

Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

Abstract translation: 一种用于操作数据处理系统的技术包括确定要从高速缓存受害的高速缓存行是否包括尚未记录的高可用性（HA）数据。 响应于确定要从缓存中受害的高速缓存线包括尚未记录的HA数据，HA数据的地址被写入HA脏地址数据结构，例如脏地址表（DAT）， 经由第一非阻塞通道在第一存储器中。 从缓存中受害的高速缓存线经由第二非阻塞通道被写入第二存储器。

公开(公告)号：US09058195B2

公开(公告)日：2015-06-16

申请号：US13778802

申请日：2013-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Geraint North ,  William J. Starke ,  Phillip G. Williams

IPC: G06F12/12 ,  G06F9/455 ,  G06F12/08 ,  G06F11/00

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F11/00 ,  G06F11/1484 ,  G06F11/202 ,  G06F11/2041 ,  G06F11/2097 ,  G06F12/0891 ,  G06F2009/45583

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache comprising a plurality of cache rows (1210), each cache row comprising a cache line (1214) and an image modification flag (1217) indicating a modification of said cache line caused by the running of the virtual machine; and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit comprises a replication manager adapted to define a log (200) in the memory prior to running the virtual machine in said first operating mode; and said cache further includes a cache controller (122) adapted to periodically check said image modification flags; write only the memory address of the flagged cache lines in the defined log and subsequently clear the image modification flags. A computer cluster including such computer systems and a method of managing such a computer cluster are also disclosed.

Abstract translation: 公开了一种包括适于以第一操作模式运行虚拟机的处理器单元（110）的计算机系统（100） 所述高速缓存包括多个高速缓存行（1210），每个高速缓存行包括高速缓存行（1214）和指示所述高速缓存行的修改的图像修改标志（1217），所述高速缓存行指示由 虚拟机的运行; 以及高速缓存控制器可访问的存储器（140），用于存储所述虚拟机的图像; 其中所述处理器单元包括适于在所述第一操作模式中运行所述虚拟机之前在所述存储器中定义日志（200）的复制管理器; 并且所述高速缓存还包括适于周期性地检查所述图像修改标志的高速缓存控制器（122） 只写入定义的日志中标记的高速缓存行的存储器地址，然后清除映像修改标志。 还公开了包括这样的计算机系统的计算机集群和管理这种计算机集群的方法。

公开(公告)号：US20150127908A1

公开(公告)日：2015-05-07

申请号：US14073531

申请日：2013-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0811

Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

Abstract translation: 一种用于操作数据处理系统的技术包括确定要从高速缓存受害的高速缓存行是否包括尚未记录的高可用性（HA）数据。 响应于确定要从缓存中受害的高速缓存线包括尚未记录的HA数据，HA数据的地址被写入HA脏地址数据结构，例如脏地址表（DAT）， 经由第一非阻塞通道在第一存储器中。 从缓存中受害的高速缓存线经由第二非阻塞通道被写入第二存储器。