公开(公告)号：US11074968B2

公开(公告)日：2021-07-27

申请号：US16692263

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： Saravanan Sethuraman ,  Karthick Rajamani ,  Venkata K. Tavva ,  Hillery Hunter ,  Chitra Subramanian

IPC: G11C11/56 ,  G11C11/406

Abstract: A system and method for storing data that includes at least one memory device having a plurality of memory cells for storing data; and a memory control circuit that manages the read current and read pulse width applied to the memory cells, wherein the at least one memory device has a read current circuit configured to utilize adjustments to at least one of the read current or the read pulse width applied to the memory cells. In response to a request to read a group of the memory cells, the memory control circuit in an example, in response to determining that a comparative temperature value exceeds a first threshold, is configured to perform at least one of reducing the read current and/or increasing the read pulse width to be applied to the group of memory devices to be read.

公开(公告)号：US10446255B2

公开(公告)日：2019-10-15

申请号：US15180624

申请日：2016-06-13

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Edgar R. Cordero ,  Stephen P. Glancy ,  Jeremy R. Neaton ,  Saravanan Sethuraman

IPC: G11C29/50 ,  G11C29/02 ,  G11C29/04 ,  G11C5/14 ,  G11C11/16 ,  G11C16/34 ,  G11C11/4099 ,  G06F11/10 ,  G11C7/10 ,  G11C29/52 ,  G11C29/44

Abstract: Embodiments herein describe a memory system that includes a DRAM module with a plurality of individual DRAM chips. In one embodiment, the DRAM chips are per DRAM addressable (PDA) so that each DRAM chip can use a respective reference voltage (VREF) value to decode received data signals (e.g., DQ or CA signals). During runtime, the VREF value can drift away from its optimal value set when the memory system is initialized. To address possible drift in VREF value, the present embodiments perform VREF calibration dynamically. To do so, the memory system monitors a predefined criteria to determine when to perform VREF calibration. To calibrate VREF value, the memory system may write transmit data and then read out the test data to determine the width of a signal eye using different VREF values. The memory system selects the VREF value that results in the widest signal eye.

公开(公告)号：US10326773B2

公开(公告)日：2019-06-18

申请号：US15288757

申请日：2016-10-07

Applicant: International Business Machines Corporation

Inventor： Saritha Arunkumar ,  Diyanesh B. Chinnakkonda Vidyapoornachary ,  Douglas J. Cowie ,  Farheen Munshi ,  Saravanan Sethuraman

IPC: H04L29/06

Abstract: Embodiments disclose systems, methods, and computer program products to perform an operation for adapting a set of devices used to authenticate a client device. The operation generally includes determining a plurality of broker devices available for attesting a location of a client device, and determining, from the available broker devices, a first and second subset of broker devices based on a credibility score determined for each of the available broker devices. The operation also includes attesting the location of the client device based on information received from the first subset of broker devices regarding devices in proximity to each of the broker devices in the first subset. The operation further includes upon determining that a number of responses with the information from at least one of the broker devices in the first subset has reached a threshold, reassigning broker devices in the first and second subsets.

公开(公告)号：US20190018712A1

公开(公告)日：2019-01-17

申请号：US15650204

申请日：2017-07-14

Applicant: International Business Machines Corporation

Inventor： Briana E. Foxworth ,  Saravanan Sethuraman ,  Kevin M. Mcilvain ,  Lucas W. Mulkey ,  Adam J. McPadden

IPC: G06F9/50 ,  G05D23/19 ,  G06F1/32

CPC classification number: G06F9/5094 ,  G05D23/19 ,  G06F1/3234 ,  G06F1/3275 ,  G06F9/5016

Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.

公开(公告)号：US20180314585A1

公开(公告)日：2018-11-01

申请号：US15969803

申请日：2018-05-03

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Saravanan Sethuraman

IPC: G06F11/07 ,  G11C11/4096 ,  G06F11/14

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/14 ,  G06F11/1423 ,  G06F11/1666 ,  G11C11/4096

Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.

公开(公告)号：US10096353B2

公开(公告)日：2018-10-09

申请号：US14074117

申请日：2013-11-07

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Carlos A. Fernandez ,  Joab D. Henderson ,  William P. Hovis ,  Jeffrey A. Sabrowski ,  Anuwat Saetow ,  Saravanan Sethuraman

IPC: G11C11/406 ,  G06F13/16

Abstract: A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.

公开(公告)号：US20180083981A1

公开(公告)日：2018-03-22

申请号：US15268897

申请日：2016-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Saritha Arunkumar ,  Diyanesh B. Chinnakkonda Vidyapoornachary ,  Saravanan Sethuraman

IPC: H04L29/06 ,  G06F17/30

CPC classification number: H04L63/107 ,  G06F17/30241 ,  G06F17/30864 ,  H04L63/06 ,  H04L63/10 ,  H04W4/00 ,  H04W12/04 ,  H04W12/06 ,  H04W12/08

Abstract: A method, computer program product, and system for authenticating a computing device by geographic attestation includes a processor utilizing executing an authentication application utilizing location services executing on the computing device to obtain location data from the location services. The processor obtains the location data and creates and encodes a data structure in a secured area of a memory; the data structure is only accessible to the authentication application. The processor transmits to an authentication server, an authentication request that includes the encoded location data, requesting access to secure content. The processor obtains a request to query identifiers proximate to the computing device for additional location information and queries the identifiers and transmits this additional location information to the authentication server. The processor receives a notification and based on obtaining the notification, erases the secured area and turns off the location services on the computing device.

公开(公告)号：US20180067874A1

公开(公告)日：2018-03-08

申请号：US15807187

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Brian J. Connolly ,  Joab D. Henderson ,  Jeffrey A. Sabrowski ,  Saravanan Sethuraman ,  Kenneth L. Wright

IPC: G06F12/14 ,  G06F21/79

CPC classification number: G06F12/1466 ,  G06F21/79

Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.

公开(公告)号：US09904611B1

公开(公告)日：2018-02-27

申请号：US15363163

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kyu-Hyoun Kim ,  Warren E. Maule ,  Kevin M. Mcilvain ,  Saravanan Sethuraman

IPC: G11C7/10 ,  G06F11/20

CPC classification number: G06F11/2094 ,  G06F2201/805

Abstract: Examples of techniques for implementing a spare data buffer in a memory are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include detecting, by a processor, a failed data buffer in a memory. The method may also include enabling, by the processor, the spare data buffer in the memory. The method may further include extending, by the processor, a buffer communication to the spare data buffer to enable the spare buffer to functionally replace the failed data buffer.

公开(公告)号：US20170293343A1

公开(公告)日：2017-10-12

申请号：US15096599

申请日：2016-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Kyu-hyoun Kim ,  Saravanan Sethuraman ,  Gary A. Tressler

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/26

CPC classification number: G06F1/3225 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3253 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0688

Abstract: A computer-implemented method for controlling power consumption in a non-volatile dual inline memory module (NVDIMM-N) may include determining, via a processor, whether the NVDIMM-N is receiving power from a main power source, inactivating, via the processor, a data bus connected to an NVDIMM-N memory group responsive to determining that the NVDIMM-N is not receiving power from the main power source, backing up data stored in the NVDIMM-N memory group, via the processor, to a non-volatile memory module integrated with the NVDIMM-N, where an NVDIMM-N controller can access the NVDIMM-N memory group while backing up, and transmitting, via the processor, a low power command to an NVDIMM-N controller to place the NVDIMM-N memory group in a low power mode.