公开(公告)号：US20160180003A1

公开(公告)日：2016-06-23

申请号：US14573535

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70066 ,  G03F7/705 ,  G03F7/70558 ,  G06F2217/12 ,  Y02P90/265

Abstract: In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, the computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines one or more exposure areas in the reticle field, and at least one lithography process parameter for each of the one or more exposure areas in the reticle field based, at least in part, on the data from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.

Abstract translation: 在确定掩模版领域中的一个或多个曝光区域和用于一个或多个曝光区域的相关光刻工艺参数的方法中，计算机接收半导体设计并将半导体设计发送到设计分析程序。 此外，计算机从设计分析程序接收数据。 此外，计算机至少部分地基于来自设计分析程序的数据来确定标线场中的一个或多个曝光区域，以及至少一个光刻处理参数，用于标线区域中的一个或多个曝光区域中的每一个的光刻处理参数 ，半导体设计，以及与设计分析程序相关联的一个或多个聚类算法。

公开(公告)号：US20150339422A1

公开(公告)日：2015-11-26

申请号：US14285719

申请日：2014-05-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768

CPC classification number: G06F17/5068 ,  G06F17/50 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level.

Abstract translation: 通过级别的设计形状被映射到上层导线级别的线级设计形状设计的针脚区域。 对于不对应于通孔级设计形状的每个针脚区域，在底层导电线路层中提供通孔捕捉设计形状。 可以调整针迹区域和通孔捕捉设计形状的形状以符合设计规则约束。 此外，针迹可以可选地移动到相邻的线级设计形状中以解决设计规则冲突。 一旦所有通孔级设计形状被相应的针脚区域替换，修改后的设计布局可以消除通孔级设计形状，从而不需要提供通孔级光刻掩模。 体现修改后的设计布局的金属互连结构可以通过采用一组硬掩模层而不使用用于通孔级的光刻掩模来形成。

公开(公告)号：US20140284813A1

公开(公告)日：2014-09-25

申请号：US13849796

申请日：2013-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Abstract translation: 提供了一种设计布局，使得下面的导线结构位于上覆导电线结构中的针脚区域的下面。 当硬掩模层中的针脚区域被多次蚀刻时，可以在下面的导电线结构和上覆导电线结构之间形成针迹引导的通孔结构。 底层导线结构和上覆导线结构中的至少一个在相同设计级别上与其它导线结构电隔离，以避免无意的电短路。

公开(公告)号：US20170277823A1

公开(公告)日：2017-09-28

申请号：US15619004

申请日：2017-06-09

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  G03F7/20 ,  H01L21/311 ,  H01L21/67 ,  H01L21/768

CPC classification number: G06F17/5081 ,  G03F7/2022 ,  G06F17/5077 ,  H01L21/31144 ,  H01L21/67063 ,  H01L21/76802 ,  H01L21/76816

Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

公开(公告)号：US20160027687A1

公开(公告)日：2016-01-28

申请号：US14873824

申请日：2015-10-02

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

Abstract translation: 提供了一种设计布局，使得下面的导线结构位于上覆导电线结构中的针脚区域的下面。 当硬掩模层中的针脚区域被多次蚀刻时，可以在下面的导电线结构和上覆导电线结构之间形成针迹引导的通孔结构。 底层导线结构和上覆导线结构中的至少一个在相同设计级别上与其它导线结构电隔离，以避免无意的电短路。

公开(公告)号：US20150255342A1

公开(公告)日：2015-09-10

申请号：US14721323

申请日：2015-05-26

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract translation: 形成集成电路器件的布线结构的方法包括在层间电介质层（ILD）内形成一条或多条铜线; 掩蔽所述一条或多条铜线的选定区域; 在所述一条或多条铜线的暴露区域上选择性地镀覆金属帽区域; 以及在所述一个或多个铜线的所述金属盖区域和未加盖的区域上形成共形绝缘体层。

公开(公告)号：US09076847B2

公开(公告)日：2015-07-07

申请号：US13744705

申请日：2013-01-18

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  James A. Culp ,  Thomas W. Dyer ,  Ronald G. Filippi ,  Stephen E. Greco ,  Naftali E. Lustig ,  Andrew H. Simon

IPC: H01L21/4763 ,  H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract translation: 形成集成电路器件的布线结构的方法包括在层间电介质层（ILD）内形成一条或多条铜线; 掩蔽所述一条或多条铜线的选定区域; 在所述一条或多条铜线的暴露区域上选择性地镀覆金属帽区域; 以及在所述一个或多个铜线的所述金属盖区域和未加盖的区域上形成共形绝缘体层。

公开(公告)号：US20150143305A1

公开(公告)日：2015-05-21

申请号：US14083578

申请日：2013-11-19

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Ian P. Stobert ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  H01L21/66

CPC classification number: G06F17/5068 ,  G03F9/7026 ,  H01L22/12 ,  H01L22/20

Abstract: A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions.

Abstract translation: 提供了在晶片表面的光刻曝光期间确定焦平面的方法。 该方法可以包括接收对应于晶片表面的表面形貌的数据，并且基于与表面形貌对应的接收数据，确定具有基本上不同的拓扑图的多个区域。 接收掩模版设计数据以在晶片表面上曝光，由此，从接收到的掩模版设计数据生成分配给所确定的多个区域中的相应一个的掩模版设计数据子集。 然后为确定的多个区域中的每一个生成最佳拟合焦平面。

公开(公告)号：US20140139236A1

公开(公告)日：2014-05-22

申请号：US13680139

申请日：2012-11-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Thomas W. Dyer ,  Stephen E. Greco

IPC: G01R27/02 ,  G01R35/00

CPC classification number: G01R35/00 ,  H01L22/34

Abstract: A test layout structure including a first series of parallel metal lines in a first level, and a first series of contact structures in a second level, the second level being positioned above the first level, the first series of contact structures being positioned at known increments, where the increments are in a direction perpendicular to a length of the first series of parallel metal lines, and where one or more of the first series of contact structures is in electrical contact with one or more of the first series of parallel metal lines.

Abstract translation: 包括第一级中的第一系列平行金属线和第二级中的第一接触结构系列的测试布局结构，所述第二级位于所述第一级上方，所述第一级接触结构以已知增量 其中所述增量在垂直于所述第一系列平行金属线的长度的方向上，并且其中所述第一系列接触结构中的一个或多个与所述第一系列平行金属线中的一个或多个电接触。