公开(公告)号：US20210175207A1

公开(公告)日：2021-06-10

申请号：US17178375

申请日：2021-02-18

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Bhupender Singh ,  Richard Francis Indyk ,  Steve Ostrander ,  Thomas Weiss ,  Mark Kapfhammer

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.

公开(公告)号：US10833051B2

公开(公告)日：2020-11-10

申请号：US16256344

申请日：2019-01-24

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Thomas Weiss ,  Thomas Anthony Wassick ,  Steve Ostrander

IPC: H01L23/00 ,  H01L25/00

Abstract: Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.

公开(公告)号：US20200303339A1

公开(公告)日：2020-09-24

申请号：US16358658

申请日：2019-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： CHARLES L. ARVIN ,  Clement J. Fortin ,  Christopher D. Muzzy ,  Krishna R. Tunga ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/532

Abstract: Disclosed are interconnects in which one substrate having a high melting temperature, lead-free solder column is joined to a second substrate having openings filled with a low melting temperature, lead-free solder such that the high melting temperature, lead-free solder column penetrates into the low melting temperature, lead-free solder so as to obtain a short moment arm of solder.

公开(公告)号：US10431563B1

公开(公告)日：2019-10-01

申请号：US15948038

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Mark W. Kapfhammer ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Thomas Weiss

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/00

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

公开(公告)号：US20190295921A1

公开(公告)日：2019-09-26

申请号：US15934972

申请日：2018-03-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Marcus E. Interrante ,  Thomas E. Lombardi ,  Hilton T. Toy ,  Krishna R. Tunga ,  Thomas Weiss

IPC: H01L23/373 ,  H05K1/02 ,  H01L23/42 ,  H01L23/538 ,  H01L23/00

Abstract: A method of managing thermal warpage of a laminate which includes: assembling a stiffener and an adhesive on the laminate, the stiffener being a material that has a higher modulus of elasticity than the laminate; applying a force to deform the laminate a predetermined amount; heating the laminate, stiffener and adhesive to a predetermined temperature at which the adhesive cures to bond the stiffener to the laminate; cooling the laminate, stiffener and adhesive to a temperature below the predetermined temperature, the laminate maintaining its deformed shape.

公开(公告)号：US10257924B2

公开(公告)日：2019-04-09

申请号：US15831534

申请日：2017-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James A. Busby ,  Silvio Dragone ,  Michael J. Fisher ,  Michael A. Gaynes ,  David C. Long ,  Kenneth P. Rodbell ,  William Santiago-Fernandez ,  Thomas Weiss

IPC: G06F21/00 ,  H05K1/02 ,  H05K1/18 ,  H05K5/02 ,  G06F21/87

Abstract: Tamper-proof electronic packages and fabrication methods are provided which include a glass enclosure enclosing, at least in part, at least one electronic component within a secure volume, and a tamper-respondent detector. The glass enclosure includes stressed glass with a compressively-stressed surface layer, and the tamper-respondent detector monitors, at least in part, the stressed glass to facilitate defining the secure volume. The stressed glass fragments with an attempted intrusion event through the stressed glass, and the tamper-respondent detector detects the fragmenting of the stressed glass. In certain embodiments, the stressed glass may be a machined glass enclosure that has undergone ion-exchange processing, and the compressively-stressed surface layer of the stressed glass may be compressively-stressed to ensure that the stressed glass fragments into glass particles of fragmentation size less than 1000 μm with the intrusion event.

公开(公告)号：US10242931B2

公开(公告)日：2019-03-26

申请号：US14936902

申请日：2015-11-10

Applicant: International Business Machines Corporation

Inventor： Raschid J. Bezama ,  David C. Long ,  Govindarajan Natarajan ,  Thomas Weiss

IPC: F28F7/00 ,  H01L23/473 ,  F28D15/00 ,  H01L23/373 ,  F28F13/00

Abstract: A heat sink and method for using the same for use in cooling an integrated circuit (IC) chip is provided herein. The heat sink includes a manifold block, a liquid-filled cooling system, and a compliant foil affixed to the manifold block and backed by a liquid in the closed loop cooling system. The pressure provided by the liquid behind the foil causes the foil to bow, and to conform to non-planarities in the surface of the IC chip, thus reducing air gaps and increasing thermal coupling between the IC chip and the heat sink.

公开(公告)号：US20190006312A1

公开(公告)日：2019-01-03

申请号：US15640475

申请日：2017-07-01

Applicant: International Business Machines Corporation

Inventor： CHARLES L. ARVIN ,  Clement Fortin ,  Christopher D. Muzzy ,  Brian W. Quinlan ,  Thomas A. Wassick ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/498

Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

公开(公告)号：US09913416B2

公开(公告)日：2018-03-06

申请号：US14941872

申请日：2015-11-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael J. Fisher ,  David C. Long ,  Michael T. Peets ,  Thomas Weiss

IPC: H05K3/02 ,  H05K13/00 ,  H05K3/10

CPC classification number: H05K13/00 ,  H05K3/10 ,  H05K5/0208

Abstract: Methods of fabricating tamper-respondent assemblies are provided which include an electronic enclosure, a tamper-respondent electronic circuit structure, and at least one security element. The electronic enclosure encloses, at least in part, at least one electronic component to be protected, and includes an inner surface. The tamper-respondent electronic circuit structure includes a tamper-respondent sensor covering, at least in part, the inner surface of the electronic enclosure, and the at least one security element overlies and physically secures in place, at least in part, the tamper-respondent sensor covering, at least in part, the inner surface of the electronic enclosure. In enhanced embodiments, the electronic enclosure is secured to a multilayer circuit board which includes an embedded tamper-respondent sensor, and together, the tamper-respondent sensor covering the inner surface of the electronic enclosure and the embedded tamper-respondent sensor within the multilayer circuit board define a secure volume about the electronic component(s).

公开(公告)号：US09894749B2

公开(公告)日：2018-02-13

申请号：US14865708

申请日：2015-09-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William L. Brodsky ,  James A. Busby ,  Zachary T. Dreiss ,  Michael J. Fisher ,  David C. Long ,  William Santiago-Fernandez ,  Thomas Weiss

IPC: G08B13/14 ,  H05K1/02 ,  H05K1/18 ,  G06F21/87 ,  H05K5/02

CPC classification number: H05K1/0213 ,  G06F21/87 ,  H05K1/0275 ,  H05K1/183 ,  H05K5/0208 ,  H05K2201/10151

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor having unexposed circuit lines forming, at least in part, one or more tamper-detect network(s), and the tamper-respondent sensor having at least one external bond region. The tamper-respondent assembly further includes at least one conductive trace and an adhesive. The conductive trace(s) forms, at least in part, the one or more tamper-detect network(s), and is exposed, at least in part, on the tamper-respondent sensor(s) within the external bond region(s). The adhesive contacts the conductive trace(s) within the external bond region(s) of the tamper-respondent sensor(s), and the adhesive, in part, facilitates securing the at least one tamper-respondent sensor within the tamper-respondent assembly. In enhanced embodiments, the conductive trace(s) is a chemically compromisable conductor susceptible to damage during a chemical attack on the adhesive within the external bond region(s).