公开(公告)号：US10516028B2

公开(公告)日：2019-12-24

申请号：US16504244

申请日：2019-07-06

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Heng Wu ,  Peng Xu

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08

Abstract: A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.

公开(公告)号：US10446647B2

公开(公告)日：2019-10-15

申请号：US15790826

申请日：2017-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/49

Abstract: A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.

公开(公告)号：US10388571B2

公开(公告)日：2019-08-20

申请号：US15982558

申请日：2018-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Thamarai S. Devarajan ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device that includes a first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region. The first plurality of fin structures includes adjacent fin structures separated by a lesser pitch than the adjacent fin structures in the second plurality of fin structures. At least one layer of dielectric material between adjacent fin structures, wherein a portion of the first plurality of fin structures extending above the at least one layer of dielectric material in the first device region is substantially equal to the portion of the second plurality of fin structures extending above the at least one layer of dielectric material in the second device region. Source and drain regions are present on opposing sides of a gate structure that is present on the fin structures.

公开(公告)号：US10381355B2

公开(公告)日：2019-08-13

申请号：US15868488

申请日：2018-01-11

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Zhenxing Bi ,  Juntao Li

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: A configuration of components formed on a semiconductor structure is provided. A non-limiting example of the configuration includes a substrate having a first section doped with a first dopant and a second section doped with a second dopant. The configuration further includes an insulator interposed between the first and second sections. A first fin extends upwardly from the first section, and second and third fins extend upwardly from the second section. A conductor is configured to be shared between proximal gates operably interposed between the first and second fins. A dielectric material is configured to separate proximal gates operably interposed between the second and third fins.

公开(公告)号：US10366928B2

公开(公告)日：2019-07-30

申请号：US15433163

申请日：2017-02-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Donald F. Canaperi ,  Thamarai S. Devarajan ,  Sivananda K. Kanakasabapathy ,  Fee Li Lie ,  Peng Xu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers.

公开(公告)号：US20190214392A1

公开(公告)日：2019-07-11

申请号：US15868488

申请日：2018-01-11

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Zhenxing Bi ,  Juntao Li

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: A configuration of components formed on a semiconductor structure is provided. A non-limiting example of the configuration includes a substrate having a first section doped with a first dopant and a second section doped with a second dopant. The configuration further includes an insulator interposed between the first and second sections. A first fin extends upwardly from the first section, and second and third fins extend upwardly from the second section. A conductor is configured to be shared between proximal gates operably interposed between the first and second fins. A dielectric material is configured to separate proximal gates operably interposed between the second and third fins.

公开(公告)号：US10332986B2

公开(公告)日：2019-06-25

申请号：US15243246

申请日：2016-08-22

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/775

Abstract: A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein.

公开(公告)号：US10332799B2

公开(公告)日：2019-06-25

申请号：US15873215

申请日：2018-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.

公开(公告)号：US10325817B2

公开(公告)日：2019-06-18

申请号：US16018921

申请日：2018-06-26

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/8238 ,  H01L21/306 ,  H01L21/762 ,  H01L27/092

Abstract: Methods are provided for fabricating semiconductor fins having uniform profiles. For example, a method includes forming semiconductor fins on a substrate, including a first semiconductor fin disposed in a first device region, and a second semiconductor fin disposed in a second device region. The first and second semiconductor fins are formed of different types of semiconductor material, and are initially formed to have different widths and heights. A semiconductor fin trimming process is performed, which is selective to the semiconductor material of the second semiconductor fin, so that the fin trimming process results in the formation of semiconductor fins having substantially equal heights and equal widths across the device regions as a result of the fin trimming process. The semiconductor fins in different device regions are initially formed with non-uniform profiles (e.g., differential heights and widths) to compensate for micro-loading and etch rate variations during the fin trimming process.

公开(公告)号：US10319813B2

公开(公告)日：2019-06-11

申请号：US15470352

申请日：2017-03-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L29/06 ,  H01L25/07 ,  H01L25/00 ,  H01L29/08 ,  H01L21/28 ,  H01L21/324

Abstract: Integrated chips and methods of forming the same include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.