公开(公告)号：US08227905B1

公开(公告)日：2012-07-24

申请号：US12931325

申请日：2011-01-27

申请人： Akito Yoshida ,  Young Wook Heo

发明人： Akito Yoshida ,  Young Wook Heo

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are reflowed and fused together.

摘要翻译： 可堆叠的半导体封装包括具有包括电路图案的第一侧表面的基板。 每个电路图案包括垫。 半导体管芯电耦合到电路图案。 密封剂在衬垫的内部覆盖半导体管芯和衬底的第一侧表面。 焊料层融合到每个焊盘。 选择直接相邻的焊盘之间的横向距离大于密封剂的侧壁与紧邻的焊盘之间的横向距离，并且焊料层相对于第一侧表面的高度被选择为小于侧壁的高度 使得堆叠在焊料层/焊盘上的半导体封装的未对准是在第二半导体封装中的焊料层和相应焊球的并置的一个被回流熔合在一起时进行自校正。

公开(公告)号：US07737542B1

公开(公告)日：2010-06-15

申请号：US12291119

申请日：2008-11-05

申请人： Akito Yoshida ,  Young Wook Heo

发明人： Akito Yoshida ,  Young Wook Heo

IPC分类号： H01L23/04 ,  H01L23/02

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stackable semiconductor package includes a substrate with a first side surface that includes circuit patterns. Each circuit pattern includes a pad. A semiconductor die is electrically coupled to the circuit patterns. An encapsulant covers the semiconductor die and the first side surface of the substrate inward of the pads. A layer of a solder is fused to each of the pads. A lateral distance between immediately adjacent pads is selected to be greater than a lateral distance between sidewalls of the encapsulant and immediately adjacent pads, and a height of the solder layers relative to the first side surface is selected to be less than a height of the sidewalls of the encapsulant, so that misalignment of a semiconductor package stacked on the solder layers/pads is self-correcting when juxtaposed ones of the solder layers and respective solder balls of the second semiconductor package are ref lowed and fused together.

摘要翻译： 可堆叠的半导体封装包括具有包括电路图案的第一侧表面的基板。 每个电路图案包括垫。 半导体管芯电耦合到电路图案。 密封剂在衬垫的内部覆盖半导体管芯和衬底的第一侧表面。 焊料层融合到每个焊盘。 选择直接相邻的焊盘之间的横向距离大于密封剂的侧壁与紧邻的焊盘之间的横向距离，并且焊料层相对于第一侧表面的高度被选择为小于侧壁的高度 使得堆叠在焊料层/焊盘上的半导体封装的未对准是在第二半导体封装的并联焊料层和相应的焊球中的并置熔合在一起时进行自校正。

公开(公告)号：US06389689B2

公开(公告)日：2002-05-21

申请号：US09024940

申请日：1998-02-17

申请人： Young Wook Heo

发明人： Young Wook Heo

IPC分类号： H05K334

CPC分类号： H01L21/561 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A method of fabricating a semiconductor package is provided, which realizes a small-size semiconductor package without performance deterioration, to meet a tendency to miniaturization of electronic products in which semiconductor packages are mounted, such as communication apparatus and computer, provides a new type of compact multi-pin semiconductor package as large as a semiconductor chip mounted thereon, and accomplishes a semiconductor package having multi-function to minimize its mounting area on an electronic product, resulting in minimizing of the products.

摘要翻译： 提供了一种制造半导体封装的方法，其实现了小型半导体封装，而没有性能劣化，以满足其中安装半导体封装的电子产品（例如通信设备和计算机）的小型化的趋势，提供了一种新型 紧凑的多引脚半导体封装与安装在其上的半导体芯片一样大，并且实现具有多功能的半导体封装以最小化其在电子产品上的安装面积，从而最小化产品。

公开(公告)号：US5977624A

公开(公告)日：1999-11-02

申请号：US8552

申请日：1998-01-16

申请人： Young Wook Heo ,  Byung Joon Han

发明人： Young Wook Heo ,  Byung Joon Han

IPC分类号： H01L23/31 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3114 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311

摘要： A chip size semiconductor package with a light, thin, simple and compact structure having a reduced size of its semiconductor chip while having an increased number of pins and without degrading its functions. For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.

摘要翻译： 具有轻，薄，简单且紧凑结构的芯片尺寸半导体封装，其半导体芯片的尺寸减小，同时具有增加的引脚数量并且不降低其功能。 对于封装，可以使用具有布置在芯片的端部上的接合焊盘的半导体芯片或具有布置在芯片的中心部分上的接合焊盘的半导体芯片。 在任一情况下，封装的输入/输出端子以区域阵列的形式布置。 因此，当将包装安装在电子设备上时，其安装面积可以最小化，从而实现最终产品的紧凑性。

公开(公告)号：US5858815A

公开(公告)日：1999-01-12

申请号：US763605

申请日：1996-12-11

申请人： Young Wook Heo ,  Byung Joon Han

发明人： Young Wook Heo ,  Byung Joon Han

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/04 ,  H01L23/31 ,  H01L21/56 ,  H01L21/58

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181

摘要： A process for manufacturing chip size semiconductor package with a light, thin, and compact structure having a reduced size of its semiconductor chip while having an increased number of pins For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.

摘要翻译： 一种用于制造具有轻薄，紧凑结构的芯片尺寸半导体封装的方法，其半导体芯片的尺寸减小，同时具有增加的引脚数对于封装，可以使用具有布置在其上的接合焊盘的半导体芯片 芯片的端部或具有布置在芯片的中心部分上的接合焊盘的半导体芯片。 在任一情况下，封装的输入/输出端子以区域阵列的形式布置。 因此，当将包装安装在电子设备上时，其安装面积可以最小化，从而实现最终产品的紧凑性。