公开(公告)号：US20190088759A1

公开(公告)日：2019-03-21

申请号：US16080824

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： SEUNG HOON SUNG ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7856

Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

公开(公告)号：US20180358440A1

公开(公告)日：2018-12-13

申请号：US15778863

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

公开(公告)号：US20160365416A1

公开(公告)日：2016-12-15

申请号：US15120803

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  WILLY RACHMADY ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  RAVI PILLARISETTY ,  ROBERT S. CHAU

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

Abstract translation: 实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。 另一实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。 本文还包括其它实施例。

公开(公告)号：US20160204246A1

公开(公告)日：2016-07-14

申请号：US14914102

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

Abstract translation: 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

公开(公告)号：US20160190319A1

公开(公告)日：2016-06-30

申请号：US14912059

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： JACK T. KAVALIEROS ,  MARKO RADOSAVLJEVIC ,  MATTHEW V. METZ ,  HAN WUI THEN ,  BENJAMIN CHU-KUNG ,  VAN H. LE ,  NILOY MUKHERJEE ,  SANSAPTAK DASGUPTA ,  RAVI PILLARISETTY ,  GILBERT DEWEY ,  ROBERT S. CHAU ,  NANCY M. ZELICK ,  WILLY RACHMADY

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/267 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a lower portion composed of a first semiconductor material with a first lattice constant (L1), and has an upper portion composed of a second semiconductor material with a second lattice constant (L2). A cladding layer is disposed on the upper portion, but not on the lower portion, of the semiconductor fin. The cladding layer is composed of a third semiconductor material with a third lattice constant (L3), wherein L3>L2>L1. A gate stack is disposed on a channel region of the cladding layer. Source/drain regions are disposed on either side of the channel region.

Abstract translation: 描述了具有多层柔性衬底的非平面半导体器件以及制造这种非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍具有由具有第一晶格常数（L1）的第一半导体材料构成的下部，并且具有由具有第二晶格常数（L2）的第二半导体材料构成的上部。 在半导体翅片的上部而不是下部设置包覆层。 包覆层由具有第三晶格常数（L3）的第三半导体材料构成，其中L3> L2> L1。 栅堆叠设置在包层的沟道区上。 源极/漏极区域设置在沟道区域的两侧。

公开(公告)号：US20200273952A1

公开(公告)日：2020-08-27

申请号：US15930627

申请日：2020-05-13

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  BENJAMIN CHU-KUNG ,  SEUNG HOON SUNG ,  JACK T. KAVALIEROS ,  TAHIR GHANI ,  HAROLD W. KENNEL

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

公开(公告)号：US20190214479A1

公开(公告)日：2019-07-11

申请号：US16326844

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  SEUNG HOON SUNG ,  BENJAMIN CHU-KUNG ,  TAHIR GHANI

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/417 ,  H01L29/785

Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.

公开(公告)号：US20180323310A1

公开(公告)日：2018-11-08

申请号：US15529432

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L29/778 ,  H01L27/06

CPC classification number: H01L29/78681 ,  H01L27/0605 ,  H01L29/1054 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170358645A1

公开(公告)日：2017-12-14

申请号：US15525269

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  GLENN A. GLASS

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/775 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

公开(公告)号：US20170345900A1

公开(公告)日：2017-11-30

申请号：US15527221

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/205 ,  H01L21/02 ,  H01L21/18

CPC classification number: H01L29/205 ,  H01L21/02455 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/182 ,  H01L21/185

Abstract: Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.