公开(公告)号：US11990403B2

公开(公告)日：2024-05-21

申请号：US17218080

申请日：2021-03-30

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Richard E. Schenker ,  Jeffery D. Bielefeld ,  Rami Hourani ,  Manish Chandhok

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5226

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US11953826B2

公开(公告)日：2024-04-09

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Robert L. Bristol ,  Marie Krysak ,  Florian Gstrein ,  Eungnak Han ,  Kevin L. Lin ,  Rami Hourani ,  Shane M. Harlson

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

CPC classification number: G03F7/0035 ,  G03F7/0002 ,  G03F7/40 ,  H01L21/027 ,  H01L21/0274 ,  H01L21/768 ,  H01L21/76802

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20230230919A1

公开(公告)日：2023-07-20

申请号：US17579249

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Nafees A. Kabir ,  Kevin L. Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/5228 ,  H01L21/76825

Abstract: An integrated circuit device includes a first interconnect layer, and a conductive first interconnect feature and a conductive second interconnect feature laterally separated by a body of insulating or semiconductor material. In an example, the first and second interconnect features are above the first interconnect layer. The integrated circuit device further includes a non-conductive feature above and on the first interconnect feature, and a conductive third interconnect feature above and on the second interconnect feature. The integrated circuit device also includes a second interconnect layer above the non-conductive feature and third interconnect features. In an example, the second and third interconnect features conductively couple the first and second interconnect layers.

公开(公告)号：US11594485B2

公开(公告)日：2023-02-28

申请号：US16430977

申请日：2019-06-04

Applicant: INTEL CORPORATION

Inventor： Kevin L. Lin ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Urusa Alaan ,  Ehren Mannebach

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105

Abstract: An integrated circuit includes a base comprising an insulating dielectric. A plurality of conductive lines extends vertically above the base in a spaced-apart arrangement, the plurality including a first conductive line and a second conductive line adjacent to the first conductive line. A void is between the first and second conductive lines. A cap of insulating material is located above the void and defines an upper boundary of the void such that the void is further located between the base and the cap of insulating material. In some embodiments, one or more vias contacts an upper end of one or more of the conductive lines.

公开(公告)号：US11462469B2

公开(公告)日：2022-10-04

申请号：US16143700

申请日：2018-09-27

Applicant: INTEL CORPORATION

Inventor： Kevin L. Lin ,  Nafees A. Kabir ,  Richard Schenker

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Techniques are disclosed that enable independent control of interconnect lines and line end structures using a single mask. The techniques provided are particularly useful, for instance, where single mask lithography processes limit the scaling of line end structures. In some embodiments, the techniques can be implemented using a liner body and multiple angled etches of the liner body to provide a line end structure comprised of a remaining portion of the liner body. In such cases, the line end structure material enables an etch rate that is slower than the etch rate of surrounding insulator materials. Furthermore, the line end structure can be of minimal size not attainable using conventional single mask processes. In other embodiments, the techniques can be implemented using a hardmask that includes hardmask features defining lines, and one or more angled etches of the hardmask to provide line end structure(s) of minimal size.

公开(公告)号：US20220216149A1

公开(公告)日：2022-07-07

申请号：US17700198

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Nicholas James Harold McKubre ,  Richard Farrington Vreeland ,  Sansaptak Dasgupta

IPC: H01L23/522 ,  H01L23/532

Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.

公开(公告)号：US20220102268A1

公开(公告)日：2022-03-31

申请号：US17033375

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Urusa Alaan ,  Kevin L. Lin ,  Miriam Reshotko ,  Sarah Atanasov ,  Christopher Jezewski ,  Carl Naylor ,  Mauro Kobrinsky ,  Hui Jae Yoo

IPC: H01L23/522 ,  H01L21/768

Abstract: Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.

公开(公告)号：US11251072B2

公开(公告)日：2022-02-15

申请号：US16346305

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Robert L. Bristol ,  James M. Blackwell ,  Rami Hourani ,  Marie Krysak

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US11137681B2

公开(公告)日：2021-10-05

申请号：US16097960

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Robert L. Bristol ,  Marie Krysak ,  Florian Gstrein ,  Eungnak Han ,  Kevin L. Lin ,  Rami Hourani ,  Shane M. Harlson

IPC: G03F7/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US11024538B2

公开(公告)日：2021-06-01

申请号：US16465526

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Tayseer Mahdi ,  Jessica M. Torres ,  Jeffery D. Bielefeld ,  Marie Krysak ,  James M. Blackwell

IPC: H01L21/768

Abstract: In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.