公开(公告)号：US20220416050A1

公开(公告)日：2022-12-29

申请号：US17359327

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Cory BOMBERGER ,  Gilbert DEWEY ,  Anand S. MURTHY ,  Mauro KOBRINSKY ,  Rushabh SHAH ,  Chi-Hing CHOI ,  Harold W. KENNEL ,  Omair SAADAT ,  Adedapo A. ONI ,  Nazila HARATIPOUR ,  Tahir GHANI

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

公开(公告)号：US20220416040A1

公开(公告)日：2022-12-29

申请号：US17357748

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Oleg GOLONZKA ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/8234

Abstract: Released fins for advanced integrated circuit structure fabrication are described. For example, an integrated circuit structure includes a sub-fin. A dielectric spacer material is on the sub-fin. A fin is on the dielectric spacer material. A void in the dielectric spacer material, the void vertically between the sub-fin and the fin.

公开(公告)号：US20220406895A1

公开(公告)日：2022-12-22

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20220399334A1

公开(公告)日：2022-12-15

申请号：US17346999

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Conor P. PULS ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

Abstract: Integrated circuit structures having backside self-aligned conductive via bars, and methods of fabricating integrated circuit structures having backside self-aligned conductive via bars, are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first gate electrode is around the first stack of nanowires. A second gate electrode is around the second stack of nanowires. A conductive trench contact structure is between the first gate electrode and the second gate electrode. A conductive via bar is on the conductive trench contact structure, the conductive via bar having a backside surface co-planar with a backside surface of the first and second sub-fin structures.

公开(公告)号：US20220393013A1

公开(公告)日：2022-12-08

申请号：US17339146

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sairam SUBRAMANIAN ,  Conor P. PULS ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is along an end of the first gate stack in the gap. A second dielectric gate spacer is along an end of the second gate stack in the gap. A dielectric material is between and in lateral contact with the first dielectric gate spacer and the second dielectric gate spacer.

公开(公告)号：US20220392896A1

公开(公告)日：2022-12-08

申请号：US17340540

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Charles H. WALLACE ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit structures having backside gate cut or backside trench contact cut, and methods of fabricating integrated circuit structures having backside gate cut or backside trench contact cut, are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first gate electrode is around the first stack of nanowires. A second gate electrode is around the second stack of nanowires. A dielectric structure is between the first gate electrode and the second gate electrode. The dielectric structure is continuous along an entirety of a height of the first gate electrode and the first sub-fin structure.

公开(公告)号：US20220336634A1

公开(公告)日：2022-10-20

申请号：US17853320

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Karthik JAMBUNATHAN ,  Biswajeet GUHA ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20220285342A1

公开(公告)日：2022-09-08

申请号：US17825664

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Yih WANG ,  Rishabh MEHANDRU ,  Mauro J. KOBRINSKY ,  Tahir GHANI ,  Mark BOHR ,  Marni NABORS

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US20220140076A1

公开(公告)日：2022-05-05

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20220093597A1

公开(公告)日：2022-03-24

申请号：US17030350

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Daniel G. OUELLETTE ,  Daniel B. O'BRIEN ,  Jeffrey S. LEIB ,  Orb ACTON ,  Lukas BAUMGARTEL ,  Dan S. LAVRIC ,  Dax M. CRUM ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/092 ,  H01L29/775 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/40

Abstract: Gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer on a first gate dielectric. The P-type conductive layer includes molybdenum and nitrogen. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer on a second gate dielectric.