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    DYNAMIC LOAD BASED MEMORY TAG MANAGEMENT
    21.
    发明申请
    DYNAMIC LOAD BASED MEMORY TAG MANAGEMENT 审中-公开

    公开(公告)号：US20180239534A1

    公开(公告)日：2018-08-23

    申请号：US15438355

    申请日：2017-02-21

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Glenn D. Gilda ,  Mark R. Hodges

    IPC分类号： G06F3/06

    CPC分类号： G06F13/1673 ,  G06F12/08 ,  G11C7/1063 ,  G11C11/4076 ,  G11C2207/2245 ,  G11C2207/2272

    摘要： A computer-implemented method for managing a memory control unit includes receiving a command at the memory control unit. The command includes a command type that either requires or does not require buffering resources. The method further includes determining, via the memory control unit, a number of available memory tags from a first set of memory tags that are associated with the buffering resources. The method includes determining, via the memory control unit, a number of available memory tags from a second set of memory tags that are not associated with the buffering resources. The method also includes dynamically adjusting, via the memory control unit, assignment of memory tags for use in the second set of memory tags based on the command type, the number of available memory tags from the first set of memory tags, and the number of available memory tags from the second set of memory tags.

    Synchronization and order detection in a memory system
    24.
    发明授权
    Synchronization and order detection in a memory system 有权
    存储系统中的同步和顺序检测

    公开(公告)号：US09430418B2

    公开(公告)日：2016-08-30

    申请号：US13835485

    申请日：2013-03-15

    申请人： International Business Machines Corporation

    发明人： Patrick J. Meaney ,  Glenn D. Gilda ,  Eric E. Retter ,  John S. Dodson ,  Gary A. Van Huben ,  Brad W. Michael ,  Stephen J. Powell

    IPC分类号： G06F1/32 ,  G06F13/16 ,  G11C7/10

    CPC分类号： G06F11/1679 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F1/32 ,  G06F11/1497 ,  G06F11/1604 ,  G06F11/1675 ,  G06F13/1689 ,  G06F13/1694 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/52

    摘要： Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

    摘要翻译： 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。

    Early data delivery prior to error detection completion
    26.
    发明授权
    Early data delivery prior to error detection completion 有权
    错误检测完成前的早期数据传送

    公开(公告)号：US09104564B2

    公开(公告)日：2015-08-11

    申请号：US14501101

    申请日：2014-09-30

    申请人： International Business Machines Corporation

    发明人： Glenn D. Gilda ,  Mark R. Hodges ,  Vesselina K. Papazova ,  Patrick J. Meaney

    IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/08

    CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/08

    摘要： A computer implemented method for early data delivery prior to error detection completion in a memory system includes receiving a frame of a multi-frame data block at a memory control unit interface. A controller writes the frame to a buffer control block in a memory controller nest domain. The frame is read from the buffer control block by a cache subsystem interface in a system domain prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame by an error detector in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to a correction pipeline in the system domain. The intercept signal indicates that error correction is needed prior to writing data in the frame to a cache subsystem.

    摘要翻译： 在存储器系统中的错误检测完成之前的用于早期数据传送的计算机实现方法包括在存储器控制单元接口处接收多帧数据块的帧。 控制器将帧写入存储器控制器嵌套域中的缓冲器控制块。 在完成多帧数据块的错误检测之前，通过系统域中的缓存子系统接口从缓冲器控制块读取该帧。 通过存储器控制器嵌套域中的错误检测器在帧上执行错误检测。 基于检测到帧中的错误，拦截信号从存储器控制器嵌套域发送到系统域中的校正流水线。 截距信号表示在将帧中的数据写入缓存子系统之前需要纠错。

    Early data delivery prior to error detection completion
    27.
    发明授权
    Early data delivery prior to error detection completion 有权
    错误检测完成前的早期数据传送

    公开(公告)号：US09092330B2

    公开(公告)日：2015-07-28

    申请号：US13834959

    申请日：2013-03-15

    申请人： International Business Machines Corporation

    发明人： Glenn D. Gilda ,  Mark R. Hodges ,  Vesselina K. Papazova ,  Patrick J. Meaney

    IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/08

    CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/08

    摘要： Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain.

    摘要翻译： 实施例涉及在存储器系统中的错误检测完成之前的早期数据传送。 一个方面是包括具有系统域中的校正流水线的缓存子系统接口的系统。 该系统包括存储器控制器嵌套域中的存储器控​​制单元接口和在系统域和存储器控制器嵌套域之间提供异步边界层的缓冲器控制块。 控制器被配置为接收多帧数据块的帧并将该帧写入缓冲器控制块。 在完成多帧数据块的错误检测之前，该帧由高速缓存子系统接口读取。 对存储器控制器嵌套域中的帧执行错误检测。 基于检测到帧中的错误，拦截信号从存储器控制器嵌套域发送到系统域中的校正流水线。

    REPLAY SUSPENSION IN A MEMORY SYSTEM
    28.
    发明申请
    REPLAY SUSPENSION IN A MEMORY SYSTEM 有权
    在记忆系统中重置暂停

    公开(公告)号：US20140281783A1

    公开(公告)日：2014-09-18

    申请号：US13835444

    申请日：2013-03-15

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Mark R. Hodges ,  Irving G. Baysah ,  John S. Dodson ,  Patrick J. Meaney ,  Glenn D. Gilda

    IPC分类号： H04L1/18 ,  G06F11/16

    CPC分类号： H04L1/1874 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/141 ,  G06F11/1625 ,  G11C7/1066 ,  G11C2211/4061 ,  H04L1/188

    摘要： Embodiments relate to replay suspension in a memory system. One aspect is a system that includes a replay buffer coupled to a memory controller interface, and a replay control coupled to the replay buffer and a memory controller. The replay control is configured to receive an error indication associated with sending data from the memory controller interface to a memory subsystem as part of an operation. A replay pending signal is provided to the memory controller based on the error indication. Based on waiting for a period of time sufficient for the memory controller to provide remaining data associated with the operation to the replay buffer, a replay signal is asserted.

    摘要翻译： 实施例涉及在存储器系统中的重放暂停。 一个方面是包括耦合到存储器控制器接口的重放缓冲器和耦合到重放缓冲器的重放控制器和存储器控制器的系统。 重播控制被配置为接收与作为操作的一部分的从存储器控制器接口发送数据到存储器子系统相关联的错误指示。 基于错误指示将重放等待信号提供给存储器控制器。 基于等待一段足以使存储器控制器向重播缓冲器提供与该操作相关联的剩余数据的时间段，断言重放信号。

    SYNCHRONIZATION AND ORDER DETECTION IN A MEMORY SYSTEM
    29.
    发明申请
    SYNCHRONIZATION AND ORDER DETECTION IN A MEMORY SYSTEM 有权
    记忆系统中的同步和顺序检测

    公开(公告)号：US20140281325A1

    公开(公告)日：2014-09-18

    申请号：US13835485

    申请日：2013-03-15

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Patrick J. Meaney ,  Glenn D. Gilda ,  Eric E. Retter ,  John S. Dodson ,  Gary A. Van Huben ,  Brad W. Michael ,  Stephen J. Powell

    IPC分类号： G11C7/22

    CPC分类号： G06F11/1679 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F1/32 ,  G06F11/1497 ,  G06F11/1604 ,  G06F11/1675 ,  G06F13/1689 ,  G06F13/1694 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/52

    摘要： Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted.

    摘要翻译： 实施例涉及存储器系统中的失步检测和失序检测。 一个方面是包括多个通道的系统，每个通道提供与存储器缓冲器芯片和多个存储器件的通信。 存储器控制单元耦合到多个通道。 存储器控制单元被配置为执行包括在两个或更多个信道上接收帧的方法。 存储器控制单元识别每个接收到的帧中的对准逻辑输入，并且基于对准逻辑输入生成针对接收帧的每个信道的对准逻辑的汇总输入。 存储器控制单元基于每个通道的偏斜值来调整定时对准。 比较每个定时调整的总结输入。 基于至少两个定时调整的总结输入之间的不匹配，断言错误信号。