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公开(公告)号：US09159410B1
公开(公告)日：2015-10-13
申请号：US14295509
申请日：2014-06-04
CPC分类号： G11C13/0026 , G11C5/02 , G11C5/025 , G11C5/06 , G11C7/12 , G11C7/18 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/78 , G11C2213/79
摘要： Embodiments of the present disclosure describe a device and methods of accessing the device. The device can include a plurality of memory cells, each cell including a plurality of resistive memory components each designed to store data as resistance and an access transistor configured to control access to the plurality of resistive memory components. A wordline is configured to enable access to the set of resistor memory components by enabling the access transistor. A plurality of bitlines are each connected to a respective and different set of resistive memory components from each of the plurality of memory cells. A bitline controller is configured to access the plurality of resistive memory components by applying a first voltage to a first set of the plurality of bitlines and a second voltage to a second set of bitlines.
摘要翻译： 本公开的实施例描述了访问设备的设备和方法。 该设备可以包括多个存储器单元，每个单元包括多个电阻存储器组件，每个电阻存储器组件被设计为将数据存储为电阻，并且存取晶体管被配置为控制对多个电阻存储器组件的访问。 字线被配置为通过启用存取晶体管来访问该组电阻器存储器组件。 多个位线各自连接到来自多个存储器单元中的每一个的相应且不同的电阻性存储器组件集合。 位线控制器被配置为通过将第一电压施加到多个位线的第一组并且将第二电压施加到第二组位线来访问多个电阻性存储器组件。
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22.发明申请ERROR FEEDBACK AND LOGGING WITH MEMORY ON-CHIP ERROR CHECKING AND CORRECTING (ECC) 有权错误反馈和记录与内存片上错误检查和更正（ECC）公开(公告)号：US20150212886A1
公开(公告)日：2015-07-30
申请号：US14320283
申请日：2014-06-30
发明人： Paul W. Coteus , Hillery C. Hunter , Charles Arthur Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Warren E. Maule , Vipinchandra Patel
IPC分类号： G06F11/10
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/1048
摘要： Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
摘要翻译： 可以在片上存储器中执行错误检查和校正（ECC），其中错误由控制器而不是片上存储器校正。 可以标记控制器以示出已经发生错误以及其在存储器中发生的位置。 控制器可以访问与错误相关联的ECC位，并可能修复不正确的数据。 可以与存储器的读取操作并行地进行错误检查，以便降低延迟。
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公开(公告)号：US20150212885A1
公开(公告)日：2015-07-30
申请号：US14168460
申请日：2014-01-30
发明人： Paul W. Coteus , Hillery C. Hunter , Charles A. Kilmer , Kyu-hyoun Kim , Luis A. Lastras-Montano , Warren E. Maule , Vipinchandra Patel
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/1048
摘要： Error checking and correcting (ECC) may be performed in an on-chip memory where an error is corrected by a controller and not the on-chip memory. The controller may be flagged to show that an error has occurred and where it has occurred in the memory. The controller may access ECC bits associated with the error and may fix incorrect data. The error checking may be done in parallel with read operations of the memory so as to lower latency.
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公开(公告)号：US20150179280A1
公开(公告)日：2015-06-25
申请号：US14138838
申请日：2013-12-23
CPC分类号： G11C29/50004 , G11C29/022 , G11C29/025 , G11C29/70 , G11C29/702 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/13188 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
摘要： A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
摘要翻译： 公开了一种用于测试连接到并布置在用于连接缺陷的逻辑芯片的顶部上的多个存储器芯片的堆叠存储器件的方法。 该方法可以包括通过将数据值写入存储器芯片中的第一位置，从第一位置读取数据值，检测第一位错误并记录第一位错误的位数来测试存储器芯片。 该方法还可以包括通过将数据值写入存储器芯片中的第二位置来测试存储器芯片，从存储器芯片中的第二位置读取数据值，检测第二位错误并记录第二位的位数 错误。 该方法还可以包括用备用连接替换与第一和第二位错误共同的连接。
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25.发明授权公开(公告)号：US11587600B2
公开(公告)日：2023-02-21
申请号：US16397154
申请日：2019-04-29
发明人： Steven R. Carlough , Susan M. Eickhoff , Warren E. Maule , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
摘要： One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
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公开(公告)号：US11586360B2
公开(公告)日：2023-02-21
申请号：US17320269
申请日：2021-05-14
IPC分类号： G06F3/06
摘要： In an approach a request to write data to memory is received, wherein the memory includes: a first set of dynamic random-access memory (DRAM) accessible via a first memory channel, and a first set of storage class (SCM) memory accessible via a second memory channel. The data is written to the first set of DRAM via the first memory channel. The data is mirrored to the first set of SCM via the second memory channel.
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公开(公告)号：US20220091927A1
公开(公告)日：2022-03-24
申请号：US17539813
申请日：2021-12-01
摘要： A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.
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公开(公告)号：US10592332B2
公开(公告)日：2020-03-17
申请号：US15967609
申请日：2018-05-01
IPC分类号： G06F11/10
摘要： An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached.
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公开(公告)号：US20200075079A1
公开(公告)日：2020-03-05
申请号：US16674235
申请日：2019-11-05
IPC分类号： G11C11/4076 , G11C11/24 , G11C11/4093 , G11C29/00 , G11C16/04 , G11C29/04 , G11C5/04
摘要： A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.
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公开(公告)号：US10453503B2
公开(公告)日：2019-10-22
申请号：US14696192
申请日：2015-04-24
IPC分类号： G11C7/10 , G06F13/16 , G11C11/408
摘要： A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.
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