公开(公告)号：US20090236651A1

公开(公告)日：2009-09-24

申请号：US12463545

申请日：2009-05-11

申请人： Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

发明人： Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC分类号： H01L27/105 ,  H01L29/788

CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

公开(公告)号：US20090159962A1

公开(公告)日：2009-06-25

申请号：US12338308

申请日：2008-12-18

申请人： Hyun Suk Kim ,  Sun-II Shim ,  Chang-Seok Kang ,  Won-Cheol Jeong ,  Jung-Dal Choi ,  Jae-Kwan Park ,  Seung-Hyun Lim ,  Sun-Jung Kim

发明人： Hyun Suk Kim ,  Sun-II Shim ,  Chang-Seok Kang ,  Won-Cheol Jeong ,  Jung-Dal Choi ,  Jae-Kwan Park ,  Seung-Hyun Lim ,  Sun-Jung Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

摘要翻译： 提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

公开(公告)号：US07544565B2

公开(公告)日：2009-06-09

申请号：US11642198

申请日：2006-12-20

申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC分类号： H01L21/8247

CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

公开(公告)号：US07419909B2

公开(公告)日：2008-09-02

申请号：US11647722

申请日：2006-12-29

申请人： Jin-Ho Kim ,  Jae-Kwan Park ,  Dong-Hwa Kwak ,  Su-Jin Ahn ,  Yoon-Moon Park ,  Jue-Hwang Sim ,  Jang-Ho Park ,  Sang-Yong Park

发明人： Jin-Ho Kim ,  Jae-Kwan Park ,  Dong-Hwa Kwak ,  Su-Jin Ahn ,  Yoon-Moon Park ,  Jue-Hwang Sim ,  Jang-Ho Park ,  Sang-Yong Park

IPC分类号： H01L21/302

CPC分类号： H01L27/11568 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/105

摘要： Patterns are formed in a semiconductor device by defining a lower layer that includes a first region and a second region on a semiconductor substrate, forming first patterns with a first pitch that extend to the first and second regions, forming second patterns with a second pitch in the second region that are alternately arranged with the first patterns, forming a space insulating layer that covers the first and second patterns and comprises gap regions that are alternately arranged with the first patterns so as to correspond with the second patterns, forming third patterns that correspond to the second patterns in the gap regions, respectively, etching the space insulating layer between the first and second patterns and between the first and third patterns, such that the space insulating layer remains between the second patterns and the third patterns, and etching the lower layer using the first, second, and third patterns and the remaining space insulating layer between the second and third patterns as an etching mask.

摘要翻译： 通过在半导体衬底上限定包括第一区域和第二区域的下层形成半导体器件中的图案，形成具有延伸到第一和第二区域的第一间距的第一图案，以第二间距形成第二图案 所述第二区域与所述第一图案交替布置，形成覆盖所述第一图案和所述第二图案的间隔绝缘层，并且包括与所述第一图案交替布置以与所述第二图案对应的间隙区域，形成与所述第二图案对应的第三图案 分别在间隙区域中蚀刻第一和第二图案之间以及第一和第三图案之间的空间绝缘层，使得空​​间绝缘层保留在第二图案和第三图案之间，并蚀刻下部 使用第一，第二和第三图案和第二个之间的剩余空间绝缘层 nd第三图案作为蚀刻掩模。

公开(公告)号：US5840591A

公开(公告)日：1998-11-24

申请号：US565029

申请日：1995-11-30

申请人： Jae-Kwan Park ,  Jong-Woo Park

发明人： Jae-Kwan Park ,  Jong-Woo Park

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/10808

摘要： A buried bit line DRAM cell and a manufacturing method thereof are provided. The buried bit line DRAM cell has a buried bit line formed into a trench which isolates devices, the buried bit line being isolated from a semiconductor substrate, a gate formed to be orthogonal to the bit line on the substrate, a first insulating layer formed to insulate the gate, a source and a drain of a transistor formed on the substrate at both sides of the gate, a self-aligned bit line contact formed between the first insulating layers for making contact between the drain and the buried bit line, and a self-aligned buried contact formed between the first insulating layers for making contact between the source and a storage electrode. According to the above structure, misalignment between the gate and the bit line and the excessive exposure to thermal processing which are inherent in conventional Buried Bit Line cells can be avoided and the design rule margin can be improved.

摘要翻译： 提供了掩埋位线DRAM单元及其制造方法。 掩埋位线DRAM单元具有形成沟槽的掩埋位线，隔离器件，掩埋位线与半导体衬底隔离，形成为与衬底上的位线正交的栅极;第一绝缘层，形成为 在门的两侧将形成在衬底上的晶体管的源极和漏极绝缘，形成在第一绝缘层之间以在漏极和掩埋位线之间接触的自对准位线接触，以及 在第一绝缘层之间形成的用于使源极与存储电极接触的自对准埋入触点。 根据上述结构，可以避免常规掩埋位线单元中固有的栅极和位线之间的偏移和过热暴露于热处理，并且可以提高设计规则裕度。

公开(公告)号：US09030884B2

公开(公告)日：2015-05-12

申请号：US13081260

申请日：2011-04-06

申请人： Jae-Kwan Park

发明人： Jae-Kwan Park

IPC分类号： G11C11/34 ,  G11C7/12 ,  G11C16/06 ,  G11C16/28

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C16/06 ,  G11C16/24 ,  G11C16/28

摘要： Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference.

摘要翻译： 描述了存储器，预充电电路和用于预充电存储器的方法。 一种这样的方法包括至少部分地基于目标电压和预充电的数据线的电压之间的电压差，向数据线提供电压并调整提供给数据线的电压。 示例性预充电电路包括电压发生器，其被配置为产生至少部分基于参考电压和反馈信号的幅度的输出电压，第一和第二驱动器以及电压检测器。 电压检测器被配置为确定参考电压和耦合到第二驱动器的数据线的采样电压之间的电压差，并且至少部分地基于该差产生反馈信号。

公开(公告)号：US08854898B2

公开(公告)日：2014-10-07

申请号：US13326199

申请日：2011-12-14

申请人： Jae-Kwan Park

发明人： Jae-Kwan Park

IPC分类号： G11C7/10

CPC分类号： G06F11/079 ,  G06F11/0727 ,  G06F11/0751 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/1063 ,  G11C29/24 ,  G11C2207/063

摘要： Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

摘要翻译： 提供了用于比较表示一组存储器单元的故障存储器单元的数量的感测电流和表示参考数量的故障存储单元的参考电流的装置和方法。 一种这样的装置包括被配置为接收感测电流并接收参考电流的比较器。 比较器包括被配置为缓冲感测电流的感测电流缓冲器，并且比较器还被配置为提供具有指示比较结果的逻辑电平的输出信号。

公开(公告)号：US20140210095A1

公开(公告)日：2014-07-31

申请号：US14227625

申请日：2014-03-27

申请人： Jang-ho Park ,  Jae-Kwan Park ,  Dong-hwa Kwak ,  So-wi Jin ,  Byung-jun Hwang ,  Nam-su Lim

发明人： Jang-ho Park ,  Jae-Kwan Park ,  Dong-hwa Kwak ,  So-wi Jin ,  Byung-jun Hwang ,  Nam-su Lim

IPC分类号： H01L27/115

CPC分类号： H01L23/48 ,  G11C5/063 ,  G11C16/0483 ,  H01L21/02697 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction

公开(公告)号：US08686563B2

公开(公告)日：2014-04-01

申请号：US12639542

申请日：2009-12-16

申请人： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

发明人： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

摘要翻译： 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US20130155780A1

公开(公告)日：2013-06-20

申请号：US13326199

申请日：2011-12-14

申请人： Jae-Kwan Park

发明人： Jae-Kwan Park

IPC分类号： G11C7/10 ,  G11C7/06

CPC分类号： G06F11/079 ,  G06F11/0727 ,  G06F11/0751 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1057 ,  G11C7/1063 ,  G11C29/24 ,  G11C2207/063

摘要： Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.

摘要翻译： 提供了用于比较表示一组存储器单元的故障存储器单元的数量的感测电流和表示参考数量的故障存储单元的参考电流的装置和方法。 一种这样的装置包括被配置为接收感测电流并接收参考电流的比较器。 比较器包括被配置为缓冲感测电流的感测电流缓冲器，并且比较器还被配置为提供具有指示比较结果的逻辑电平的输出信号。