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32 条记录 (耗时 0.026 秒)

    Semiconductor memory device with uniform data access time
    21.
    发明申请
    Semiconductor memory device with uniform data access time 有权
    具有统一数据存取时间的半导体存储器

    公开(公告)号：US20050141255A1

    公开(公告)日：2005-06-30

    申请号：US11023659

    申请日：2004-12-29

    申请人： Jae-Bum Ko ,  Sang-Hoon Hong ,  Se-Jun Kim

    发明人： Jae-Bum Ko ,  Sang-Hoon Hong ,  Se-Jun Kim

    IPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C8/12

    CPC分类号： G11C8/12 ,  G11C5/025 ,  G11C5/063 ,  G11C2207/105

    摘要： A semiconductor memory device includes: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one row address control unit and two column address control units; and a peripheral region having two pad groups, wherein two pad groups are respectively located at the opposite side of the core region.

    摘要翻译： 半导体存储器件包括：具有多个存储体组的核心区域，用于响应于输入的地址输出/存储数据，其中每个存储体组包括一个存储体，一个行地址控制单元和两个列地址控制单元; 以及具有两个焊盘组的周边区域，其中两个焊盘组分别位于芯区域的相对侧。

    Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package
    22.
    发明申请
    Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package 失效
    半导体存储器件，具有多芯片封装中I / O焊盘的高效复用

    公开(公告)号：US20050141254A1

    公开(公告)日：2005-06-30

    申请号：US11015421

    申请日：2004-12-20

    申请人： Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    发明人： Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    IPC分类号： G11C7/00 ,  G11C5/02 ,  G11C5/06

    CPC分类号： G11C5/066

    摘要： A semiconductor memory device includes: a memory core area; a plurality of address input pads for transferring addresses; a first address buffer part for receiving the addresses and outputting first addresses; a plurality of multi I/O pads for inputting/outputting data or inputting/outputting addresses/data while multiplexing the addresses/data; a data I/O buffer part for receiving data from the plurality of multi I/O pads and transferring the data to the memory core area or receiving and outputting addresses; a second address buffer part for receiving the addresses from the data I/O buffer part and outputting second addresses; an address multiplexer part for combining the first addresses and the second addresses and outputting data access addresses to the memory core area; and a path control part for controlling the address multiplexer part.

    摘要翻译： 半导体存储器件包括：存储器核心区域; 用于传送地址的多个地址输入板; 第一地址缓冲部分，用于接收地址并输出第一地址; 用于在复用地址/数据的同时输入/输出数据或输入/输出地址/数据的多个多I / O焊盘; 数据I / O缓冲器部分，用于从多个多I / O焊盘接收数据并将数据传送到存储器核心区域或接收和输出地址; 第二地址缓冲器部分，用于从数据I / O缓冲器部分接收地址并输出第二地址; 地址多路复用器部分，用于组合第一地址和第二地址，并将数据访问地址输出到存储器核心区域; 以及用于控制地址多路复用器部分的路径控制部分。

    Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package
    23.
    发明授权
    Semiconductor memory device with efficient multiplexing of I/O pad in multi-chip package 失效
    半导体存储器件，具有多芯片封装中I / O焊盘的高效复用

    公开(公告)号：US07057964B2

    公开(公告)日：2006-06-06

    申请号：US11015421

    申请日：2004-12-20

    申请人： Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    发明人： Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    IPC分类号： G11C8/00

    CPC分类号： G11C5/066

    摘要： A semiconductor memory device includes: a memory core area; a plurality of address input pads for transferring addresses; a first address buffer part for receiving the addresses and outputting first addresses; a plurality of multi I/O pads for inputting/outputting data or inputting/outputting addresses/data while multiplexing the addresses/data; a data I/O buffer part for receiving data from the plurality of multi I/O pads and transferring the data to the memory core area or receiving and outputting addresses; a second address buffer part for receiving the addresses from the data I/O buffer part and outputting second addresses; an address multiplexer part for combining the first addresses and the second addresses and outputting data access addresses to the memory core area; and a path control part for controlling the address multiplexer part.

    摘要翻译： 半导体存储器件包括：存储器核心区域; 用于传送地址的多个地址输入板; 第一地址缓冲部分，用于接收地址并输出第一地址; 用于在复用地址/数据的同时输入/输出数据或输入/输出地址/数据的多个多I / O焊盘; 数据I / O缓冲器部分，用于从多个多I / O焊盘接收数据并将数据传送到存储器核心区域或接收和输出地址; 第二地址缓冲器部分，用于从数据I / O缓冲器部分接收地址并输出第二地址; 地址多路复用器部分，用于组合第一地址和第二地址，并将数据访问地址输出到存储器核心区域; 以及用于控制地址多路复用器部分的路径控制部分。

    ANALOG-TO-DIGITAL CONVERTER
    24.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER 有权
    模拟数字转换器

    公开(公告)号：US20050184897A1

    公开(公告)日：2005-08-25

    申请号：US11021963

    申请日：2004-12-23

    申请人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

    发明人： Se-Jun Kim ,  Sang-Hoon Hong ,  Jae-Bum Ko

    IPC分类号： H03M1/06 ,  H03M1/48 ,  H03M1/68 ,  H03M1/66 ,  H03M1/00 ,  H03M1/12

    CPC分类号： H03M1/0607 ,  H03M1/48 ,  H03M1/687

    摘要： An analog-to-digital converter outputs a reliable digital value corresponding to an input analog value without regard to variation of process, temperature and driving voltage. The analog-to-digital converter includes a voltage comparator for comparing an input voltage with a comparison voltage, a binary up/down counter for up/down converting an outputted binary digital code based on the comparison result of the voltage comparator, a digital-to-analog converting unit for converting the binary digital code that is transferred from the up/down counter as the comparison voltage by using a bias voltage and an offset voltage and for outputting a feedback upper threshold voltage and a feedback lower threshold voltage, and a feedback bias unit for comparing the feedback upper threshold voltage with an upper threshold voltage having the maximum level of the input voltage to output the bias voltage and comparing the feedback lower threshold voltage with a lower threshold voltage having the minimum level of the input voltage to output the offset voltage.

    摘要翻译： 模数转换器输出对应于输入模拟值的可靠数字值，而不考虑过程，温度和驱动电压的变化。 模数转换器包括用于将输入电压与比较电压进行比较的电压比较器，用于根据电压比较器的比较结果对输出的二进制数字代码进行上/下转换的二进制递增/递减计数器， 模拟转换单元，用于通过使用偏置电压和偏移电压来转换从上/下计数器传送的二进制数字代码作为比较电压，并输出反馈上阈值电压和反馈下阈值电压，以及 反馈偏置单元，用于将反馈上阈值电压与具有输入电压的最大电平的上阈值电压进行比较，以输出偏置电压，并将反馈下阈值电压与具有输入电压的最小电平的较低阈值电压进行比较以输出 偏移电压。

    Semiconductor memory device for controlling cell block with state machine
    25.
    发明申请
    Semiconductor memory device for controlling cell block with state machine 失效
    用状态机控制电池块的半导体存储器件

    公开(公告)号：US20050141299A1

    公开(公告)日：2005-06-30

    申请号：US11015475

    申请日：2004-12-20

    申请人： Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    发明人： Sang-Hoon Hong ,  Jae-Bum Ko ,  Se-Jun Kim

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G11C29/00

    CPC分类号： G11C7/22 ,  G11C8/12

    摘要： A semiconductor memory device for an effective data access operation includes a cell area having N+1 number of unit cell blocks, each including M number of word lines, for storing a data in a unit cell corresponding to an inputted address; N+1 number of unit controlling blocks having respective state machines and corresponding to the respective N+1 unit cell blocks for controlling a data restoration that is accessed from a first unit cell block selected from the N+1 unit cell blocks into the first unit cell block or a second unit cell block; and a driving controlling block for controlling the N+1 unit cell blocks so that the N+1 unit controlling means are in one of first to fourth operation states.

    摘要翻译： 一种用于有效数据存取操作的半导体存储器件包括：具有N + 1个单位单元块数量的单元区域，每个单元单元块包括M个字线，用于存储与输入地址对应的单位单元中的数据; N + 1个单元控制块，具有各自的状态机，并且对应于用于控制从从N + 1个单元块选择的第一单元单元块访问到第一单元的数据恢复的相应N + 1个单位单元块 单元块或第二单元单元块; 以及驱动控制块，用于控制N + 1个单元块，使得N + 1单元控制装置处于第一至第四操作状态之一。

    DRAM for high-speed data access
    26.
    发明授权
    DRAM for high-speed data access 失效
    DRAM用于高速数据访问

    公开(公告)号：US07277977B2

    公开(公告)日：2007-10-02

    申请号：US10330482

    申请日：2002-12-30

    申请人： Jeong-Hoon Kook ,  Sang-Hoon Hong ,  Se-Jun Kim

    发明人： Jeong-Hoon Kook ,  Sang-Hoon Hong ,  Se-Jun Kim

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0893 ,  G06F12/0607 ,  G06F2212/3042 ,  G11C11/4076 ,  G11C2207/2245

    摘要： A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.

    摘要翻译： 具有用于数据输入/输出的通用交织方案的DRAM使用正常的存储体结构。 DRAM提供高性能而不考虑数据访问模式。 为了实现高性能，DRAM包括多个正常库，至少一个与正常库具有相同数据访问方案的高速缓存组，用于选择性地以读取模式选择存储与正常存储库的数据;以及 控制器，用于在连续读取命令发生到所选择的法线段时控制对高速缓存组和所选择的法线库的访问。

    Duty cycle correction circuit and delay locked loop having the same
    27.
    发明授权
    Duty cycle correction circuit and delay locked loop having the same 失效
    占空比校正电路和延迟锁定环具有相同的作用

    公开(公告)号：US06859081B2

    公开(公告)日：2005-02-22

    申请号：US10638994

    申请日：2003-08-11

    申请人： Sang-Hoon Hong ,  Se-Jun Kim ,  Jeong-Hoon Kook

    发明人： Sang-Hoon Hong ,  Se-Jun Kim ,  Jeong-Hoon Kook

    IPC分类号： H03L7/08 ,  H03K5/156 ,  H03L7/081 ,  H03L7/089 ,  H03K3/017

    CPC分类号： H03L7/0805 ,  H03K5/1565 ,  H03L7/0812 ,  H03L7/0891

    摘要： A duty cycle correction (DCC) circuit including first and second clock dividers for dividing ordinary and sub-input clocks. Optional first and second variable delay devices delay the divided clocks. First and second mixers mix an optionally delayed ordinary divided clock and sub-ordinary divided clock, or an ordinary divided clock and an optionally delayed sub-ordinary divided clock. A logic combination device is included to produce a clock at the same frequency as the ordinary and sub-input clocks, with a corrected duty cycle.

    摘要翻译： 一种占空比校正（DCC）电路，包括用于分割普通和子输入时钟的第一和第二时钟分频器。 可选的第一和第二可变延迟器件延迟分频时钟。 第一和第二混频器混合可选地延迟的普通分频时钟和次普通分频时钟，或普通分频时钟和可选延迟的次普通分频时钟。 包括逻辑组合装置以产生与正常和子输入时钟相同频率的时钟，具有校正的占空比。

    Array substrate of liquid crystal display device having thin film transistor on color filter structure and method of fabricating the same
    29.
    发明授权
    Array substrate of liquid crystal display device having thin film transistor on color filter structure and method of fabricating the same 有权
    在滤色器结构上具有薄膜晶体管的液晶显示装置的阵列基板及其制造方法

    公开(公告)号：US06912024B2

    公开(公告)日：2005-06-28

    申请号：US10716562

    申请日：2003-11-20

    申请人： Se-Jun Kim ,  Seung-Ryul Park

    发明人： Se-Jun Kim ,  Seung-Ryul Park

    IPC分类号： G02F1/136 ,  G02F1/1362 ,  G02F1/1335

    CPC分类号： G02F1/1362 ,  G02F1/136227 ,  G02F2001/136222

    摘要： An array substrate of a liquid crystal display device having a thin film transistor on a color filter structure and a method of fabricating the same are disclosed in the present invention. The liquid crystal display device having a thin film transistor on color filter structure array substrate includes a gate line and a gate electrode on a substrate, the gate line and the gate electrode being formed of a light-shielding material, a color filter layer on the substrate, covering edge portions of the gate line and the gate electrode, an overcoat layer over the substrate covering the color filter, the overcoat layer having openings exposing portions of the gate line and the gate electrode, a gate insulating layer on the overcoat layer, the color filter layer, the gate line, and the gate electrode, a semiconductor layer on the gate insulating layer, wherein the semiconductor layer has a width smaller than the gate electrode, source and drain electrodes on the gate insulating layer, contacting portions of the semiconductor layer, wherein the gate electrode, the semiconductor layer, the source electrode, and the drain electrode constitute a thin film transistor, a data line on the gate insulating layer, extending from the source electrode, crossing the gate line, and defining a pixel region, a passivation layer covering the thin film transistor and the data line and having a drain contact hole exposing a portion of the drain electrode, and a pixel electrode on the passivation layer, contacting the drain electrode through the drain contact hole.

    摘要翻译： 在本发明中公开了具有滤色器结构上的薄膜晶体管的液晶显示装置的阵列基板及其制造方法。 在滤色器结构阵列基板上具有薄膜晶体管的液晶显示装置在基板上具有栅极线和栅电极，栅极线和栅电极由遮光材料形成，滤色器层 基板，栅极线和栅电极的覆盖边缘部分，覆盖滤色器的基板上的外涂层，覆盖层具有露出栅极线和栅电极的部分的开口，外涂层上的栅极绝缘层， 所述滤色器层，所述栅极线和所述栅极电极，所述栅极绝缘层上的半导体层，其中所述半导体层的宽度小于所述栅极电极，所述栅极绝缘层上的源极和漏极，所述栅极绝缘层的接触部分 半导体层，其中栅电极，半导体层，源电极和漏电极构成薄膜晶体管，数据线在 所述栅极绝缘层从所述源极延伸，与所述栅极线交叉并且限定像素区域，覆盖所述薄膜晶体管和所述数据线的钝化层，并且具有暴露所述漏极的一部分的漏极接触孔，以及 钝化层上的像素电极，通过漏极接触孔与漏电极接触。