公开(公告)号：US20060097375A1

公开(公告)日：2006-05-11

申请号：US11320314

申请日：2005-12-27

申请人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin Wood

发明人： Mark Bohr ,  Jun He ,  Fay Hua ,  Dustin Wood

IPC分类号： H01L23/02

CPC分类号： H01L23/5382 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first and second electric current pathway between the integrated circuit and package substrate. The shunt provides a third electric current pathway between the first bump and the second bump.

公开(公告)号：USD965692S1

公开(公告)日：2022-10-04

申请号：US29819424

申请日：2021-12-15

申请人： Jun He

设计人： Jun He

公开(公告)号：US08704336B2

公开(公告)日：2014-04-22

申请号：US11848879

申请日：2007-08-31

申请人： Jun He ,  Kevin J. Lee ,  Subhash Joshi

发明人： Jun He ,  Kevin J. Lee ,  Subhash Joshi

IPC分类号： H01L23/544

CPC分类号： H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

摘要： Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region.

摘要翻译： 通常描述从划线区域选择性地去除片上再分布互连材料。 在一个示例中，一种装置包括具有再分布层的第一半导体管芯，其包括再分布电介质和一个或多个再分布金属互连，与第一半导体管芯耦合的第二半导体管芯，第二半导体管芯具有包括再分布电介质的再分配层和一个 或更多的再分配金属互连，以及设置在第一半导体管芯和第二半导体管芯之间的划线区域，划分线区域具有大部分或基本上全部的再分布电介质或再分配金属或其合适的组合， 通过划线区划分。

公开(公告)号：US08435410B2

公开(公告)日：2013-05-07

申请号：US12922357

申请日：2009-03-30

申请人： Shahab Ahmed Shamsi ,  Congying Gu ,  Jun He

发明人： Shahab Ahmed Shamsi ,  Congying Gu ,  Jun He

IPC分类号： B01D15/08

CPC分类号： C08J9/127 ,  B01J20/261 ,  B01J20/267 ,  B01J20/28042 ,  B01J20/285 ,  B01J2220/82 ,  G01N2030/528

摘要： A method for making a surfactant-based monolithic column is provided. The method comprises providing a mixture comprising at least one surfactant monomer, at least one crosslinker, at least one initiator, and at least one porogen and polymerizing the mixture to form the surfactant-based monolithic column. The present disclosure also provides a surfactant-based monolithic column, a method for separating molecules, and a process for preparing a surfactant monomer.

摘要翻译： 提供了制备基于表面活性剂的整体柱的方法。 该方法包括提供包含至少一种表面活性剂单体，至少一种交联剂，至少一种引发剂和至少一种致孔剂的混合物，并使混合物聚合以形成基于表面活性剂的整体柱。 本公开还提供了一种基于表面活性剂的整体柱，分离分子的方法和制备表面活性剂单体的方法。

公开(公告)号：US20120007242A1

公开(公告)日：2012-01-12

申请号：US13242988

申请日：2011-09-23

申请人： Jun He ,  Kevin J. Fischer ,  Ying Zhou ,  Peter K. Moon

发明人： Jun He ,  Kevin J. Fischer ,  Ying Zhou ,  Peter K. Moon

IPC分类号： H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/0217 ,  H01L21/02252 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

摘要翻译： 制造用于微电子器件的封盖互连的方法，其包括封盖层和互连件之间的任何间隙的密封特征以及由其形成的结构。 密封特征改善了互连的封装，其基本上减少或防止导电材料从封盖互连件的电迁移和/或扩散。

公开(公告)号：US20110138396A1

公开(公告)日：2011-06-09

申请号：US12955280

申请日：2010-11-29

申请人： Qi Chen ,  Jun He ,  Guang Lei Li ,  Huo Ding Li ,  Wei Liu

发明人： Qi Chen ,  Jun He ,  Guang Lei Li ,  Huo Ding Li ,  Wei Liu

IPC分类号： G06F9/46

CPC分类号： G06F9/5066

摘要： The present invention discloses a method and system for data distribution in a High-Performance Computing cluster, the High-Performance Computing cluster comprising a Management node and M computation nodes where M is an integer greater than or equal to 2, the Management node distributing the specified data to the M computation nodes, the method comprising steps of: dividing the M computation nodes into m layers where m is an integer greater than or equal to 2; dividing the specified data into k shares where k is an integer greater than or equal to 2; distributing, by the Management node, the k shares of data to a first layer of computation nodes as sub-nodes thereof, each of the first layer of computation nodes obtaining at least one share of data therein; distributing, by each of the computation nodes, the at least one share of data distributed by a parent node thereof to sub-computation nodes thereof; and requesting, by each of the computation nodes, the remaining specified data to other computation nodes, to thereby obtain all the specified data. The method and system enable data to be distributed rapidly to various computation nodes in the High-Performance Computing cluster.

摘要翻译： 本发明公开了一种高性能计算集群中数据分发的方法和系统，该高性能计算集群包括管理节点和M个计算节点，其中M为大于或等于2的整数，管理节点分发 指定的数据到M个计算节点，该方法包括以下步骤：将M个计算节点划分为m个层，其中m是大于或等于2的整数; 将指定的数据划分为k个共享，其中k是大于或等于2的整数; 由管理节点将k份数据分配给第一层计算节点作为其子节点，第一层计算节点中的每一个在其中获得至少一份数据; 由每个计算节点将由其父节点分发的数据的至少一个共享分配给其子计算节点; 并且通过每个计算节点向其他计算节点请求剩余的指定数据，从而获得所有指定的数据。 该方法和系统将数据快速分发到高性能计算集群中的各种计算节点。

公开(公告)号：US20070238309A1

公开(公告)日：2007-10-11

申请号：US11394913

申请日：2006-03-31

申请人： Jun He ,  Kevin Fischer

发明人： Jun He ,  Kevin Fischer

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76843 ,  H01L21/76832 ,  H01L21/76849

摘要： A method is described of reducing the line to line capacitance within semiconductor devices and a device demonstrating the same. The device includes a spacer layer disposed between an etch stop material and a conductive layer. Separating the etch stop layer from the conductive layers by the spacer layer may decrease the line to line capacitance significantly in a semiconductor device.

摘要翻译： 描述了一种降低半导体器件内的线间电容的方法和展示其的器件。 该器件包括设置在蚀刻停止材料和导电层之间的间隔层。 通过间隔层将蚀刻停止层与导电层分离可以在半导体器件中显着地减小线对电容。

公开(公告)号：US07175970B2

公开(公告)日：2007-02-13

申请号：US11286783

申请日：2005-11-22

申请人： Jun He ,  Jihperng Leu

发明人： Jun He ,  Jihperng Leu

IPC分类号： G03C5/00 ,  H01L21/31

CPC分类号： H01L21/76831 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S430/143 ,  H01L2924/00

摘要： In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.

摘要翻译： 在一个实施例中，在电介质层中的光致抗蚀剂（PR）沟槽图案的通孔上方形成沟槽。 沟槽由两个侧壁部分和基部限定。 通过使用PR沟槽图案作为掩模的后处理对侧壁的基部进行局部处理，以增强在基部下方的介电层的部分的机械强度。 种子和阻挡层沉积在沟槽和通孔上。 沟槽和通孔填充有金属层。 在另一个实施例中，沟槽由电介质层中的PR沟槽图案形成。 沉积并蚀刻柱PR以限定具有柱表面的柱开口。 通过后处理在柱面上局部处理立柱开口，以提高柱表面下方的电介质层的部分的机械强度。

公开(公告)号：US20060220197A1

公开(公告)日：2006-10-05

申请号：US11081187

申请日：2005-03-16

申请人： Mauro Kobrinsky ,  Jun He ,  Kevin O'Brien ,  Patrick Morrow ,  Ying Zhou ,  Shriram Ramanathan

发明人： Mauro Kobrinsky ,  Jun He ,  Kevin O'Brien ,  Patrick Morrow ,  Ying Zhou ,  Shriram Ramanathan

IPC分类号： H01L23/02

CPC分类号： H01L21/76867 ,  B23K35/302 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76888 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/48 ,  H01L2924/013

摘要： A method of forming self-passivating interconnects. At least one of two mating bond structures is formed, at least in part, from an alloy of a first metal and a second metal (or other element). The second metal is capable of migrating through the first metal to free surfaces of the mating bond structures. During bonding, the two mating bond structures are bonded together to form an interconnect, and the second metal segregates to free surfaces of this interconnect to form a passivation layer. Other embodiments are described and claimed.

摘要翻译： 一种形成自钝化互连的方法。 至少部分地由第一金属和第二金属（或其它元素）的合金形成两个匹配结合结构中的至少一个。 第二金属能够通过第一金属迁移到配合结合结构的自由表面。 在接合期间，两个配对结合结构结合在一起以形成互连，并且第二金属分离到该互连的自由表面以形成钝化层。 描述和要求保护其他实施例。

公开(公告)号：US06998868B2

公开(公告)日：2006-02-14

申请号：US10967172

申请日：2004-10-19

申请人： Jun He ,  Dong Li ,  DeXue Leng ,  Mon Chin Tsai

发明人： Jun He ,  Dong Li ,  DeXue Leng ,  Mon Chin Tsai

IPC分类号： G01R31/26

CPC分类号： H01L27/11 ,  G01R31/2853 ,  G01R31/2884 ,  G11C11/41 ,  G11C29/006 ,  G11C2029/0403 ,  G11C2029/5602 ,  H01L22/34

摘要： A test key for bridging and continuity testing is provided, comprising at least one test unit, which is composed of a first strand and a second strand embedded or non-touching intertwined with each other. The strand comprising a closed hook, a corresponding extension and a corresponding connection. The corresponding connections are electrically connected to an external voltage by at least one test pad, wherein the closed hook of the first strand is parallel with the closed hook of the second strand. A first corner is formed between the closed hooks and the corresponding extension, causing the closed hook of the first strands to be adjacent and parallel with the closed hook and the extension of the second strand. Moreover, another corner is formed between the extension and the corresponding connection, causing the connection of the first strand to be adjacent and parallel with the extension of second strand, forming an intertwining pattern.

摘要翻译： 提供了用于桥接和连续性测试的测试键，包括至少一个测试单元，该测试单元由彼此缠结的第一股和第二股嵌入或非接触组成。 绞线包括闭合的钩子，相应的延伸部分和对应的连接部分。 相应的连接通过至少一个测试垫电连接到外部电压，其中第一股线的闭合的钩子与第二股线的闭合的钩子平行。 在闭合的钩和相应的延伸部之间形成第一角，使得第一股线的闭合钩相邻并且与闭合的钩子平行并且第二股线的延伸。 此外，在延伸部和相应的连接件之间形成另一个角，使得第一股线与第二股线的延伸部相邻并平行，形成交织图案。