公开(公告)号：US20050073020A1

公开(公告)日：2005-04-07

申请号：US10709988

申请日：2004-06-11

申请人： Chi Chang

发明人： Chi Chang

IPC分类号： H01L23/50 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/50 ,  H01L23/525 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An input/output structure for a die to support an Accelerated Graphic Port (AGP) standard and a Peripheral Component Interconnection Express (PCIE) standard is provided. The I/O structure is suitable for the die pad. It comprises: a PCIE input/output pad for supporting PCIE standard; an AGP input/output pad for supporting AGP standard; a die pad coupled to an external circuit; a first conducting distributed wire coupled to the PCIE input/output pad and the die pad; and a second conducting distributed wire coupled to the AGP input/output pad and the die pad; wherein only one of the PCIE input/output pad and the AGP input/output pad is enabled at the same time.

摘要翻译： 提供了用于支持加速图形端口（AGP）标准和外围组件互连Express（PCIE）标准的芯片的输入/输出结构。 I / O结构适用于管芯焊盘。 它包括：用于支持PCIE标准的PCIE输入/输出板; 用于支持AGP标准的AGP输入/输出板; 耦合到外部电路的管芯焊盘; 耦合到PCIE输入/输出焊盘和管芯焊盘的第一导电分布线; 以及耦合到所述AGP输入/输出焊盘和所述管芯焊盘的第二导电分布导线; 其中只有一个PCIE输入/输出焊盘和AGP输入/输出焊盘同时被使能。

公开(公告)号：US06806155B1

公开(公告)日：2004-10-19

申请号：US10150255

申请日：2002-05-15

申请人： Kelwin Ko ,  Chi Chang

发明人： Kelwin Ko ,  Chi Chang

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L21/823425 ,  H01L21/823468

摘要： A method and system for providing a semiconductor device are described. The method and system include providing a plurality of gate stacks and a first source drain halo implant. The first source and drain halo implant uses the plurality of gate stacks as a mask. The method and system also include providing a lightly doped source and drain implant and a N+ source and drain implant. The source connection implant is for connecting a portion of the plurality of sources. The second source and drain implant uses the plurality of gate stacks as a mask. Moreover, CoSi formed on the source region provides a lower resistence for lines connecting the sources, allowing a lower dose to be used for the N+ source and drain implant.

摘要翻译： 描述了一种用于提供半导体器件的方法和系统。 该方法和系统包括提供多个栅极堆叠和第一源极漏极注入。 第一源极和漏极晕轮植入物使用多个栅极堆叠作为掩模。 该方法和系统还包括提供轻掺杂的源极和漏极注入以及N +源极和漏极植入物。 源连接植入物用于连接多个源的一部分。 第二源极和漏极注入使用多个栅极叠层作为掩模。 此外，形成在源极区上的CoSi对连接源的线路提供较低的电阻，允许较低剂量用于N +源极和漏极植入物。

公开(公告)号：US06664191B1

公开(公告)日：2003-12-16

申请号：US09973131

申请日：2001-10-09

申请人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

发明人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

IPC分类号： H01L21302

CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

摘要翻译： 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

公开(公告)号：US06524914B1

公开(公告)日：2003-02-25

申请号：US09699972

申请日：2000-10-30

申请人： Yue-song He ,  Sameer Haddad ,  Timothy Thurgate ,  Chi Chang

发明人： Yue-song He ,  Sameer Haddad ,  Timothy Thurgate ,  Chi Chang

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L29/66833

摘要： One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.

摘要翻译： 本发明的一个方面涉及一种制造闪存单元的方法，所述闪存单元包括以下步骤：提供其上具有闪存单元的基板; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 清洗基材; 以及植入第二类型的介质剂量漏极注入以在所述衬底中邻近所述闪存单元形成源极区域和漏极区域。

公开(公告)号：US06510085B1

公开(公告)日：2003-01-21

申请号：US09861031

申请日：2001-05-18

申请人： Richard Fastow ,  Sheunghee Park ,  Zhigang Wang ,  Sameer Haddad ,  Chi Chang

发明人： Richard Fastow ,  Sheunghee Park ,  Zhigang Wang ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404

摘要： Methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during both programming and soft programming while maintaining fast programming speeds. During programming, a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts; is applied to the drain, a voltage of between 0.5 and 2.0 volts is applied to the source and a voltage of between minus 2 and minus 0.5 volts is applied to the substrate of the selected cell to be programmed. During soft programming, a voltage of between 0.5 and 4.5 volts is applied to the control gates, between 4 and 5.5 volts is applied to the drains, between 0.5 and 2 volts is applied to the sources and between minus 2.0 and minus 0.5 volts is applied to the substrates of the memory cells.

摘要翻译： 编程和软编程短节目NOR闪存单元的方法，可在编程和软编程期间减少编程电流和列泄漏，同时保持快速的编程速度。 在编程期间，7至10伏之间的电压施加到控制栅极，电压在4和6伏之间; 施加到漏极，将0.5至2.0伏之间的电压施加到源极，并且在所述要编程的所选择的单元的衬底之间施加负2和负0.5伏之间的电压。 在软编程期间，向控制栅极施加0.5至4.5伏之间的电压，在漏极之间施加4至5.5伏之间的电压，施加0.5至2伏之间的电压，并施加负2.0至负0.5伏之间 到存储单元的基板。

公开(公告)号：US06469939B1

公开(公告)日：2002-10-22

申请号：US09969572

申请日：2001-10-01

申请人： Zhigang Wang ,  Richard Fastow ,  Sheung-Hee Park ,  Sameer S. Haddad ,  Chi Chang

发明人： Zhigang Wang ,  Richard Fastow ,  Sheung-Hee Park ,  Sameer S. Haddad ,  Chi Chang

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404

摘要： A source resistor or a positive voltage is coupled to the source and a negative bias voltage is applied at the substrate or p-well of flash memory cells for enhanced efficiency during programming and/or during an APDE (Automatic Program Disturb after Erase) process for a flash memory device. Furthermore, in a system and method for programming the flash memory device, a flash memory cell of the array of multiple flash memory cells is selected to be programmed. A control gate programming voltage is applied to the control gate of the selected flash memory cell, and a bit line programming voltage is applied to the drain of the selected flash memory cell via the common bit line terminal to which the drain of the selected flash memory cell is connected.

摘要翻译： 源极电阻或正电压耦合到源极，并且在闪存单元的衬底或p阱处施加负偏置电压，以在编程期间和/或在APDE（擦除后自动程序干扰）处理期间提高效率 闪存设备。 此外，在用于对闪速存储器件进行编程的系统和方法中，选择多个闪速存储器单元的阵列中的闪存单元进行编程。 控制栅极编程电压被施加到所选择的闪速存储器单元的控制栅极，并且位线编程电压通过公共位线端子被施加到所选择的闪存单元的漏极，所述公共位线端子选择闪存的漏极 单元格已连接。

公开(公告)号：US06444539B1

公开(公告)日：2002-09-03

申请号：US09784892

申请日：2001-02-15

申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

IPC分类号： H01L2176

CPC分类号： H01L21/7621 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76232

摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

公开(公告)号：US06252276B1

公开(公告)日：2001-06-26

申请号：US09377183

申请日：1999-08-19

申请人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

发明人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

IPC分类号： H01L2978

CPC分类号： H01L21/28202 ,  H01L21/28273 ,  H01L29/518 ,  H01L29/66825

摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.

摘要翻译： 提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。 有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。 这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

公开(公告)号：US6160317A

公开(公告)日：2000-12-12

申请号：US336057

申请日：1999-06-18

申请人： Yu Sun ,  Chi Chang ,  Mark T. Ramsbey

发明人： Yu Sun ,  Chi Chang ,  Mark T. Ramsbey

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L27/088

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.

摘要翻译： 本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。 该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。 根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

公开(公告)号：US6080639A

公开(公告)日：2000-06-27

申请号：US199265

申请日：1998-11-25

申请人： Richard J. Huang ,  Chi Chang

发明人： Richard J. Huang ,  Chi Chang

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/8247 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31625 ,  H01L21/76202 ,  H01L21/76235

摘要： Void formation is avoided without thermal treatment by a gap filling between electrically conductive elements such as stacked gates which are formed atop of isolation regions, with an oxide layer using a HDP technique. The oxide layer is doped with phosphorus to getter mobile ionic contaminants.

摘要翻译： 通过在形成于隔离区域顶部的层叠栅极之间的导电元件之间的间隙填充，使用HDP技术的氧化物层，避免了空隙形成。 氧化物层掺杂磷以吸收移动离子污染物。