Determining One or More Characteristics of a Pattern of Interest on a Specimen
    23.
    发明申请
    Determining One or More Characteristics of a Pattern of Interest on a Specimen 审中-公开
    确定样本的兴趣模式的一个或多个特征

    公开(公告)号:US20170059491A1

    公开(公告)日:2017-03-02

    申请号:US15243809

    申请日:2016-08-22

    Abstract: Methods and systems for determining characteristic(s) of patterns of interest (POIs) are provided. One system is configured to acquire output of an inspection system generated at the POI instances without detecting defects at the POI instances. The output is then used to generate a selection of the POI instances. The system then acquires output from an output acquisition subsystem for the selected POI instances. The system also determines characteristic(s) of the POI using the output acquired from the output acquisition subsystem.

    Abstract translation: 提供了用于确定感兴趣模式(POI)特征的方法和系统。 一个系统被配置为获取在POI实例处生成的检查系统的输出,而不检测POI实例的缺陷。 然后,输出用于生成POI实例的选择。 然后,系统从所选POI实例的输出采集子系统获取输出。 该系统还使用从输出采集子系统获得的输出来确定POI的特性。

    Alteration for wafer inspection
    24.
    发明授权
    Alteration for wafer inspection 有权
    晶圆检查更改

    公开(公告)号:US08826200B2

    公开(公告)日:2014-09-02

    申请号:US13893267

    申请日:2013-05-13

    CPC classification number: G06F17/5045 G01N21/956 G06F17/5081 G06F2217/14

    Abstract: Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.

    Abstract translation: 提供了一种用于对晶片上的缺陷进行合并的方法和系统。 一种方法包括识别在晶片上制造的器件层的设计领域,其对于制造器件的制造不是至关重要的,并且通过从该设计中消除所识别的区域中的特征,从而为该层产生改变的设计 层。 该方法还包括使用改变的设计将层上检测到的缺陷分组成组,使得每个组中的缺陷的改变设计中的特征至少相似。

    Method and System for Weak Pattern Quantification

    公开(公告)号:US20180174797A1

    公开(公告)日:2018-06-21

    申请号:US15729458

    申请日:2017-10-10

    Abstract: A weak pattern identification method includes acquiring inspection data from a set of patterns on a wafer, identifying failing pattern types on the wafer, and grouping like pattern types of the failing pattern types into a set of pattern groups. The weak pattern identification method also includes acquiring image data from multiple varied instances of a first pattern type grouped in a first group, wherein the multiple varied instances of the first pattern type are formed under different conditions. The weak pattern identification method also includes comparing images obtained from common structures of the instances of the first pattern type to identify local differences within a portion of the first pattern type. Further, the weak pattern identification method includes identifying metrology sites within the portion of the first pattern type proximate to a location of the local differences within the portion of the first pattern type.

    Method and system for universal target based inspection and metrology
    28.
    发明授权
    Method and system for universal target based inspection and metrology 有权
    通用目标检测和计量方法与系统

    公开(公告)号:US09576861B2

    公开(公告)日:2017-02-21

    申请号:US14083126

    申请日:2013-11-18

    CPC classification number: H01L22/12 G06F17/5081

    Abstract: Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.

    Abstract translation: 通用的基于目标的检测驱动度量包括设计多个通过检测工具测量的通用度量目标并且可以用计量工具测量,使用设计数据识别晶片的至少一个管芯内的多个检查特征,将多个通用目标 在晶片的至少一个模具内,每个通用目标被设置为至少接近所识别的可检查特征之一,用检查工具检查包含一个或多个通用目标的区域,以识别一个或多个异常通用目标 检查区域具有检查工具,并且响应于在被检查区域中识别一个或多个异常通用目标,对所述一个或多个异常通用度量目标与计量工具执行一个或多个计量过程。

    Inspection guided overlay metrology
    29.
    发明授权
    Inspection guided overlay metrology 有权
    检验指导覆盖计量

    公开(公告)号:US09170209B1

    公开(公告)日:2015-10-27

    申请号:US14053193

    申请日:2013-10-14

    Abstract: Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

    Abstract translation: 检查引导覆盖度量可以包括执行图案搜索以便识别半导体晶片上的预定图案,为半导体晶片上的预定图案的所有实例生成护理区域,通过执行检查扫描来检查所产生的护理区域内的缺陷 每个生成的护理区域,其中检查扫描包括低阈值或高灵敏度检查扫描,识别具有大于使用缺陷检查技术的所选覆盖规格的测量的覆盖误差的半导体晶片的预定图案的覆盖位置 将生成的护理区域的所识别的缺陷的位置数据与生成的护理区域内的所识别的覆盖位置的位置数据进行比较,以便识别其中缺陷接近所识别的覆盖位置的一个或多个位置,以及生成计量取样 基于确定的位置进行计划。

    Pattern Failure Discovery by Leveraging Nominal Characteristics of Alternating Failure Modes
    30.
    发明申请
    Pattern Failure Discovery by Leveraging Nominal Characteristics of Alternating Failure Modes 有权
    通过利用交替故障模式的标称特性发现模式故障

    公开(公告)号:US20150199803A1

    公开(公告)日:2015-07-16

    申请号:US14542430

    申请日:2014-11-14

    Inventor: Allen Park

    CPC classification number: G06T7/001 G06T2207/30148 H01L21/67288

    Abstract: Methods and systems for detecting defects on a wafer are provided. One method includes acquiring output for a wafer generated by an inspection system. Different dies are printed on the wafer with different process conditions. The different process conditions correspond to different failure modes for the wafer. The method also includes comparing the output generated for a first of the different dies printed with the different process conditions corresponding to a first of the different failure modes with the output generated for a second of the different dies printed with the different process conditions corresponding to a second of the different failure modes opposite to the first of the different failure modes. In addition, the method includes detecting defects on the wafer based on results of the comparing step.

    Abstract translation: 提供了用于检测晶片上的缺陷的方法和系统。 一种方法包括获取由检查系统产生的晶片的输出。 在不同的工艺条件下在晶片上印刷不同的模具。 不同的工艺条件对应于晶片的不同故障模式。 该方法还包括将针对不同工艺条件印刷的不同模具中的第一种不同的不同模具产生的输出与对应于不同工艺条件的不同工艺条件相对应地印刷在不同模具中的第二种模具 与第一种不同故障模式相反的不同故障模式的第二种。 此外,该方法包括基于比较步骤的结果检测晶片上的缺陷。

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