公开(公告)号：US10290088B2

公开(公告)日：2019-05-14

申请号：US14209198

申请日：2014-03-13

Applicant: KLA-Tencor Corporation

Inventor： Himanshu Vajaria ,  Tommaso Torelli ,  Bradley Ries ,  Mohan Mahadevan

IPC: G06T7/00 ,  H01L21/66

Abstract: Methods and systems for monitoring process tool conditions are disclosed. The method combines single wafer, multiple wafers within a single lot and multiple lot information together statistically as input to a custom classification engine that can consume single or multiple scan, channel, wafer and lot to determine process tool status.

公开(公告)号：US20180003648A1

公开(公告)日：2018-01-04

申请号：US15692863

申请日：2017-08-31

Applicant: KLA-Tencor Corporation

Inventor： Lena Nicolaides ,  Mohan Mahadevan ,  Alex Salnik ,  Scott A. Young

IPC: G01N21/95 ,  G01N21/17 ,  G01N21/88

Abstract: Disclosed are methods and apparatus for detecting defects or reviewing defects in a semiconductor sample. The system has a brightfield (BF) module for directing a BF illumination beam onto a sample and detecting an output beam reflected from the sample in response to the BF illumination beam. The system has a modulated optical reflectance (MOR) module for directing a pump and probe beam to the sample and detecting a MOR output beam from the probe spot in response to the pump beam and the probe beam. The system includes a processor for analyzing the BF output beam from a plurality of BF spots to detect defects on a surface or near the surface of the sample and analyzing the MOR output beam from a plurality of probe spots to detect defects that are below the surface of the sample.

公开(公告)号：US09734568B2

公开(公告)日：2017-08-15

申请号：US14630252

申请日：2015-02-24

Applicant: KLA-TENCOR CORPORATION

Inventor： Himanshu Vajaria ,  Sina Jahanbin ,  Bradley Ries ,  Mohan Mahadevan

IPC: G06K9/00 ,  G06T7/00 ,  G01N21/95 ,  G06K9/48 ,  G06K9/62 ,  G06T7/13 ,  G06T7/62

CPC classification number: G06T7/0004 ,  G01N21/9503 ,  G06K9/481 ,  G06K9/6204 ,  G06K2209/19 ,  G06T7/0006 ,  G06T7/13 ,  G06T7/62 ,  G06T2207/10024 ,  G06T2207/30148

Abstract: Shadow-grams are used for edge inspection and metrology of a stacked wafer. The system includes a light source that directs collimated light at an edge of the stacked wafer, a detector opposite the light source, and a controller connected to the detector. The stacked wafer can rotate with respect to the light source. The controller analyzes a shadow-gram image of the edge of the stacked wafer. Measurements of a silhouette of the stacked wafer in the shadow-gram image are compared to predetermined measurements. Multiple shadow-gram images at different points along the edge of the stacked wafer can be aggregated and analyzed.

公开(公告)号：US09569834B2

公开(公告)日：2017-02-14

申请号：US14746820

申请日：2015-06-22

Applicant: KLA-TENCOR CORPORATION

Inventor： Himanshu Vajaria ,  Shabnam Ghadar ,  Tommaso Torelli ,  Bradley Ries ,  Mohan Mahadevan ,  Stilian Pandev

IPC: G06K9/00 ,  G06T7/00

CPC classification number: G06T7/11 ,  G06T7/001 ,  G06T2207/30148

Abstract: Methods and devices are disclosed for automated detection of a status of wafer fabrication process based on images. The methods advantageously use segment masks to enhance the signal-to-noise ratio of the images. Metrics are then calculated for the segment mask variations in order to determine one or more combinations of segment masks and metrics that are predictive of a process non-compliance. A model can be generated as a result of the process. In another embodiment, a method uses a model to monitor a process for compliance.

Abstract translation: 公开了用于基于图像自动检测晶片制造过程的状态的方法和装置。 这些方法有利地使用段掩模来增强图像的信噪比。 然后针对段掩码变化计算度量，以便确定预测过程不合规性的段掩码和度量的一个或多个组合。 作为过程的结果可以生成模型。 在另一个实施例中，一种方法使用模型来监视合规性的过程。

公开(公告)号：US11237872B2

公开(公告)日：2022-02-01

申请号：US15978626

申请日：2018-05-14

Applicant: KLA-TENCOR CORPORATION

Inventor： Ajay Gupta ,  Sankar Venkataraman ,  Sashi Balasingam ,  Mohan Mahadevan

IPC: G06F9/50 ,  G06F9/48

Abstract: Real-time job distribution software architectures for high bandwidth, hybrid processor computation systems for semiconductor inspection and metrology are disclosed. The imaging processing computer architecture can be scalable by changing the number of CPUs and GPUs to meet computing needs. The architecture is defined using a master node and one or more worker nodes to run image processing jobs in parallel for maximum throughput. The master node can receive input image data from a semiconductor wafer or reticle. Jobs based on the input image data are distributed to one of the worker nodes. Each worker node can include at least one CPU and at least one GPU. The image processing job can contain multiple tasks, and each of the tasks can be assigned to one of the CPU or GPU in the worker node using a worker job manager to process the image.

公开(公告)号：US10360477B2

公开(公告)日：2019-07-23

申请号：US15402169

申请日：2017-01-09

Applicant: KLA-Tencor Corporation

Inventor： Kris Bhaskar ,  Scott Young ,  Mark Roulo ,  Jing Zhang ,  Laurent Karsenti ,  Mohan Mahadevan ,  Bjorn Brauer

IPC: G06K9/00 ,  G06K9/62 ,  G06K9/66 ,  G06T7/00

Abstract: Methods and systems for performing one or more functions for a specimen using output simulated for the specimen are provided. One system includes one or more computer subsystems configured for acquiring output generated for a specimen by one or more detectors included in a tool configured to perform a process on the specimen. The system also includes one or more components executed by the one or more computer subsystems. The one or more components include a learning based model configured for performing one or more first functions using the acquired output as input to thereby generate simulated output for the specimen. The one or more computer subsystems are also configured for performing one or more second functions for the specimen using the simulated output.

公开(公告)号：US20180341525A1

公开(公告)日：2018-11-29

申请号：US15978626

申请日：2018-05-14

Applicant: KLA-TENCOR CORPORATION

Inventor： Ajay Gupta ,  Sankar Venkataraman ,  Sashi Balasingam ,  Mohan Mahadevan

IPC: G06F9/50 ,  G06F9/48

Abstract: Real-time job distribution software architectures for high bandwidth, hybrid processor computation systems for semiconductor inspection and metrology are disclosed. The imaging processing computer architecture can be scalable by changing the number of CPUs and GPUs to meet computing needs. The architecture is defined using a master node and one or more worker nodes to run image processing jobs in parallel for maximum throughput. The master node can receive input image data from a semiconductor wafer or reticle. Jobs based on the input image data are distributed to one of the worker nodes. Each worker node can include at least one CPU and at least one GPU. The image processing job can contain multiple tasks, and each of the tasks can be assigned to one of the CPU or GPU in the worker node using a worker job manager to process the image.

公开(公告)号：US20180293721A1

公开(公告)日：2018-10-11

申请号：US15896060

申请日：2018-02-14

Applicant: KLA-Tencor Corporation

Inventor： Ajay Gupta ,  Mohan Mahadevan ,  Sankar Venkataraman ,  Hedong Yang ,  Laurent Karsenti ,  Yair Carmon ,  Noga Bullkich ,  Udy Danino

IPC: G06T7/00 ,  G06T7/564 ,  G01N21/95 ,  G01N21/956 ,  G01N21/88

CPC classification number: G06T7/001 ,  G01N21/8851 ,  G01N21/9501 ,  G01N21/956 ,  G01N21/95607 ,  G01N2021/8867 ,  G01N2021/8887 ,  G05B19/41875 ,  G06N20/00 ,  G06T7/564 ,  G06T2207/10061 ,  G06T2207/20081 ,  G06T2207/20084 ,  G06T2207/30148 ,  H01L22/12 ,  H01L22/20

Abstract: Methods and systems for detecting defects in patterns formed on a specimen are provided. One system includes one or more components executed by one or more computer subsystems, and the component(s) include first and second learning based models. The first learning based model generates simulated contours for the patterns based on a design for the specimen, and the simulated contours are expected contours of a defect free version of the patterns in images of the specimen generated by an imaging subsystem. The second learning based model is configured for generating actual contours for the patterns in at least one acquired image of the patterns formed on the specimen. The computer subsystem(s) are configured for comparing the actual contours to the simulated contours and detecting defects in the patterns formed on the specimen based on results of the comparing.

公开(公告)号：US09645097B2

公开(公告)日：2017-05-09

申请号：US14741866

申请日：2015-06-17

Applicant: KLA-Tencor Corporation

Inventor： Lena Nicolaides ,  Ben-ming Benjamin Tsai ,  Prashant A. Aji ,  Michael Gasvoda ,  Stanley E. Stokowski ,  Guoheng Zhao ,  Youxian Wen ,  Mohan Mahadevan ,  Paul D. Horn ,  Wolfgang Vollrath ,  Isabella T. Lewis

IPC: G03B27/52 ,  G03B27/32 ,  G01N21/95 ,  G03F7/20 ,  H01L21/66

CPC classification number: G01N21/9503 ,  G01N2201/06113 ,  G03F7/7085 ,  H01L22/12

Abstract: Disclosed are methods and apparatus for inspecting and processing semiconductor wafers. The system includes an edge detection system for receiving each wafer that is to undergo a photolithography process. The edge detection system comprises an illumination channel for directing one or more illumination beams towards a side, top, and bottom edge portion that are within a border region of the wafer. The edge detection system also includes a collection module for collecting and sensing output radiation that is scattered or reflected from the edge portion of the wafer and an analyzer module for locating defects in the edge portion and determining whether each wafer is within specification based on the sensed output radiation for such wafer. The photolithography system is configured for receiving from the edge detection system each wafer that has been found to be within specification. The edge detection system is coupled in-line with the photolithography system.

公开(公告)号：US20150226676A1

公开(公告)日：2015-08-13

申请号：US14618586

申请日：2015-02-10

Applicant: KLA-Tencor Corporation

Inventor： Lena Nicolaides ,  Mohan Mahadevan ,  Alex Salnik ,  Scott A. Young

IPC: G01N21/88 ,  G01N21/95

CPC classification number: G01N21/9505 ,  G01N21/1717 ,  G01N21/9501 ,  G01N2021/8825 ,  G01N2201/06113

Abstract: Disclosed are methods and apparatus for detecting defects or reviewing defects in a semiconductor sample. The system has a brightfield (BF) module for directing a BF illumination beam onto a sample and detecting an output beam reflected from the sample in response to the BF illumination beam. The system has a modulated optical reflectance (MOR) module for directing a pump and probe beam to the sample and detecting a MOR output beam from the probe spot in response to the pump beam and the probe beam. The system includes a processor for analyzing the BF output beam from a plurality of BF spots to detect defects on a surface or near the surface of the sample and analyzing the MOR output beam from a plurality of probe spots to detect defects that are below the surface of the sample.

Abstract translation: 公开了用于检测半导体样品中的缺陷或检​​查缺陷的方法和装置。 该系统具有用于将BF照明光束引导到样品上并且响应于BF照明光束检测从样品反射的输出光束的亮场（BF）模块。 该系统具有调制的光反射（MOR）模块，用于将泵和探针光束引导到样品，并响应于泵浦光束和探针光束检测来自探针光点的MOR输出光束。 该系统包括用于分析来自多个BF点的BF输出光束的处理器，以检测样品表面或表面附近的缺陷，并分析来自多个探针点的MOR输出光束以检测低于表面的缺陷 的样品。