公开(公告)号：US07709320B2

公开(公告)日：2010-05-04

申请号：US11427065

申请日：2006-06-28

申请人： Kangguo Cheng ,  Xi Li

发明人： Kangguo Cheng ,  Xi Li

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087

摘要： A method of forming a trench capacitor and memory cells using the trench capacitor. The method includes: forming an opening in a masking layer; and forming a trench in the substrate through the opening, the trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into the substrate, the upper region of the trench adjacent to the top surface of the substrate having a vertical sidewall profile and a first width in the horizontal direction, the middle region of the trench having a tapered sidewall profile, a width in a horizontal direction of the middle region at a juncture of the upper region and the middle region being the first width and being greater than a second width in the horizontal direction of the middle region at a juncture of the middle region and the lower region.

摘要翻译： 使用沟槽电容器形成沟槽电容器和存储单元的方法。 该方法包括：在掩模层中形成开口; 并且通过所述开口在所述衬底中形成沟槽，所述沟槽具有连续的上部，中部和下部区域，所述沟槽从所述衬底的顶表面延伸到衬底中，所述沟槽的上部区域与衬底的顶表面相邻 具有垂直侧壁轮廓和在水平方向上的第一宽度，沟槽的中间区域具有锥形侧壁轮廓，在上部区域和中间区域的接合处的中间区域的水平方向上的宽度是第一 宽度，并且在中间区域和下部区域的接合处，在中间区域的水平方向上大于第二宽度。

公开(公告)号：US20080001196A1

公开(公告)日：2008-01-03

申请号：US11427065

申请日：2006-06-28

申请人： Kangguo Cheng ,  Xi Li

发明人： Kangguo Cheng ,  Xi Li

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087

摘要： A trench structure, a method of forming the trench structure, a memory cell using the trench structure and a method of forming a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.

摘要翻译： 沟槽结构，形成沟槽结构的方法，使用沟槽结构的存储单元以及使用沟槽结构形成存储单元的方法。 沟槽结构包括：衬底; 具有连续的上，中和下区域的沟槽，所述沟槽从所述衬底的顶表面延伸到所述衬底中; 所述沟槽的上部区域具有垂直侧壁轮廓; 并且沟槽的中间区域具有锥形侧壁轮廓。

公开(公告)号：US08829612B2

公开(公告)日：2014-09-09

申请号：US12983477

申请日：2011-01-03

申请人： Kangguo Cheng ,  Xi Li ,  Richard Stephen Wise

发明人： Kangguo Cheng ,  Xi Li ,  Richard Stephen Wise

IPC分类号： H01L29/66

CPC分类号： H01L21/67069 ,  H01J37/32733 ,  H01J2237/20207 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/78654

摘要： A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

摘要翻译： 制造不对称间隔物的方法，使用不对称间隔物制造的结构和用于制造不对称间隔物的装置。 该方法包括：在基底上形成具有顶表面和相对的第一和第二侧壁并具有平行于侧壁的纵向轴线的结构; 在所述基底的顶表面，所述结构的顶表面和所述结构的侧壁上形成共形层; 相对于反应离子通量使基板围绕纵向轴线倾斜，反应离子的流量以锐角撞击共形层; 以及将所述共形层暴露于所述反应离子的通量，直到所述共形层从所述结构的顶表面去除并且所述衬底的顶表面在所述第一侧壁上留下第一间隔物，并且在所述第二侧壁上留下第二间隔物，所述第一 间隔物比第二间隔物薄。

公开(公告)号：US08021945B2

公开(公告)日：2011-09-20

申请号：US12423242

申请日：2009-04-14

申请人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

发明人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

IPC分类号： H01L21/8242

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/82 ,  Y10S438/964

摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

摘要翻译： 根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。 在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。 沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。 然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。 然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。 在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。 去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。

公开(公告)号：US07893480B2

公开(公告)日：2011-02-22

申请号：US12651608

申请日：2010-01-04

申请人： Xi Li ,  Kangguo Cheng ,  Johnathan Faltermeier

发明人： Xi Li ,  Kangguo Cheng ,  Johnathan Faltermeier

IPC分类号： H01L29/94 ,  H01L27/108

CPC分类号： H01L29/945 ,  H01L21/32137 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1087 ,  H01L29/66181

摘要： A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

摘要翻译： 描述半导体结构。 该结构包括形成在具有绝缘体上半导体（SOI）层和掩埋绝缘（BOX）层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料，所述填充材料在所述沟槽存储单元内形成“V”形，其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。 还描述了制造半导体结构的方法。 该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层，使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。

公开(公告)号：US07888722B2

公开(公告)日：2011-02-15

申请号：US12138536

申请日：2008-06-13

申请人： Kangguo Cheng ,  Xi Li

发明人： Kangguo Cheng ,  Xi Li

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087

摘要： A trench structure and a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile.

摘要翻译： 沟槽结构和使用沟槽结构的存储单元。 沟槽结构包括：衬底; 具有连续的上，中和下区域的沟槽，所述沟槽从所述衬底的顶表面延伸到所述衬底中; 所述沟槽的上部区域具有垂直侧壁轮廓; 并且沟槽的中间区域具有锥形侧壁轮廓。

公开(公告)号：US20100258904A1

公开(公告)日：2010-10-14

申请号：US12423242

申请日：2009-04-14

申请人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

发明人： Xi Li ,  Russell H. Arndt ,  Kangguo Cheng ,  Richard O. Henry ,  Jinghong H. Li

IPC分类号： H01L27/07 ,  H01L21/02

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/82 ,  Y10S438/964

摘要： In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

摘要翻译： 根据本发明的一个方面，提供一种用于制造包括沟槽电容器的半导体芯片的方法。 在这种方法中，可以通过电介质层中的开口在垂直方向上蚀刻单晶半导体区域，以形成露出单晶半导体材料的粗糙表面的沟槽。 沟槽在垂直于垂直方向的第一方向上具有初始侧向尺寸。 然后在晶体表面上暴露的半导体材料以结晶方向依赖的方式进行蚀刻，以在沟槽表面暴露半导体材料的多个晶面。 然后可以沉积含掺杂剂的衬里以对沟槽的表面进行排列，然后升高衬底的温度以将掺杂剂从含掺杂剂的衬里驱动到与表面相邻的半导体区域中。 在这样的步骤中，通常暴露在壁处的半导体材料的一部分被氧化。 去除至少一些氧化部分以露出扩大的沟槽的壁，沿着该壁形成介电层和导电材料以形成沟槽电容器。

公开(公告)号：US20090184392A1

公开(公告)日：2009-07-23

申请号：US12017154

申请日：2008-01-21

申请人： Kangguo Cheng ,  Xi Li ,  Richard Wise

发明人： Kangguo Cheng ,  Xi Li ,  Richard Wise

IPC分类号： H01L21/8239 ,  H01L29/92 ,  G06F17/50

CPC分类号： H01L21/26586 ,  H01L27/10867 ,  H01L29/7833

摘要： A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided. The device structure includes a semiconductor substrate having a deep trench therein; and a first conductive layer and a second conductive layer sequentially disposed on said deep trench, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate.

摘要翻译： 提供了一种形成具有单面埋入带的沟槽器件结构的方法。 该方法包括在半导体衬底中形成深沟槽，所述深沟槽具有第一侧部分和第二侧部分; 在所述深沟槽上沉积节点电介质，其中所述节点电介质覆盖所述第一侧部分和所述第二侧部分; 在所述节点电介质上沉积第一导电层; 以一定角度进行离子注入或离子轰击到所述节点电介质的一部分中，从而从所述深沟槽的所述第一侧部分移除所述节点电介质的所述部分; 以及在所述第一导电层上沉积第二导电层，其中所述第二导电层超出所述半导体衬底的一部分。 还提供了具有单面埋置带的沟槽器件结构。 该器件结构包括其中具有深沟槽的半导体衬底; 以及顺序地设置在所述深沟槽上的第一导电层和第二导电层，其中所述第二导电层向外延伸到所述半导体衬底的一部分中。

公开(公告)号：US20080122030A1

公开(公告)日：2008-05-29

申请号：US11468472

申请日：2006-08-30

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L29/86 ,  H01L21/441

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

摘要翻译： 公开了用于增强沟槽电容的方法和如此形成的沟槽电容器。 在一个实施例中，一种方法包括形成沟槽的第一部分; 在所述第一部分中沉积介电层; 执行包括第一阶段的反应离子蚀刻以蚀刻所述电介质层并在所述沟槽的第一部分的底表面上形成微掩模，以及形成具有粗糙侧壁的所述沟槽的第二部分; 沉积节点电介质; 并用导体填充沟槽。 粗糙的侧壁增加沟槽电容，而不增加处理复杂性或成本。

公开(公告)号：US20080076230A1

公开(公告)日：2008-03-27

申请号：US11533928

申请日：2006-09-21

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Xi Li

IPC分类号： H01L21/20

CPC分类号： H01L29/945 ,  H01L29/66181

摘要： A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper portion of the bottle shaped trench above the initial conductor. Then, the method simultaneously etches a center portion of the insulating collar and the initial conductor until the void is exposed. This etching process forms a center opening within the insulating collar and the initial conductor. Additional conductor is deposited in the center opening such that the additional conductor is formed at least to the level of the surface of the substrate.

摘要翻译： 一种方法在瓶形沟槽中形成节点电介质，然后将初始导体沉积在瓶形沟槽的下部，使得在初始导体内形成空隙。 接下来，该方法在初始导体上方的瓶形沟槽的上部形成绝缘套环。 然后，该方法同时蚀刻绝缘套环的中心部分和初始导体，直到暴露出空隙。 该蚀刻工艺在绝缘环和初始导体内形成中心开口。 附加导体沉积在中心开口中，使得附加导体至少形成至基底表面的水平。