公开(公告)号：US20070023875A1

公开(公告)日：2007-02-01

申请号：US11490116

申请日：2006-07-21

申请人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Oonishi ,  Atsushi Yoshimura

发明人： Noboru Okane ,  Ryoji Matsushima ,  Kazuhiro Yamamori ,  Junya Sagara ,  Yoshio Iizuka ,  Kuniyuki Oonishi ,  Atsushi Yoshimura

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.

摘要翻译： 半导体封装包括具有元件安装部分和引线部分的引线框架。 第一半导体元件和第二半导体元件依次堆叠在元件安装部的至少一侧的主表面上。 用作第二粘合剂层的绝缘树脂层填充在第一半导体元件和第二半导体元件之间。 连接到第一半导体元件的第一接合线的元件侧端部埋设在绝缘树脂层中。

公开(公告)号：US20060139893A1

公开(公告)日：2006-06-29

申请号：US11132290

申请日：2005-05-19

申请人： Atsushi Yoshimura ,  Naoyuki Komuta ,  Hideo Numata

发明人： Atsushi Yoshimura ,  Naoyuki Komuta ,  Hideo Numata

IPC分类号： H05K7/00

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.

公开(公告)号：US20060038275A1

公开(公告)日：2006-02-23

申请号：US11200037

申请日：2005-08-10

申请人： Atsushi Yoshimura

发明人： Atsushi Yoshimura

IPC分类号： H01L23/02 ,  H01L23/52

CPC分类号： H01L25/50 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/92247

摘要： A method of manufacturing a stacked-type semiconductor device, comprises: arranging a plurality of stacked chips obtained by stacking semiconductor chips on a plurality of stages on a support substrate; connecting a semiconductor chip of each stage in each stacked chip and the support substrate by wire while performing heating in units of stacked chips; performing plastic molding of each stacked chip; and separating the stacked chips from each other. An apparatus for manufacturing a stacked-type semiconductor device, comprising divided heater blocks formed under a support substrate on which a plurality of stacked chips obtained by stacking a plurality of semiconductor chips are arranged, the divided heater blocks being formed with respect to the stacked chips, and a heating device to selectively transmit heat to a stacked chip subjected to a wire bonding.

摘要翻译： 一种层叠型半导体器件的制造方法，其特征在于，具有：将多个堆叠的芯片配置在支撑基板上的多个级上堆叠半导体芯片而得到的堆叠芯片; 在堆叠的芯片的单元中进行加热时，通过线将每个堆叠的芯片中的每个级的半导体芯片和支撑基板连接; 执行每个堆叠芯片的塑料模制; 并将堆叠的芯片彼此分离。 一种叠层型半导体器件的制造装置，其特征在于，具有形成在支撑基板的下方的分割加热块，在所述支撑基板上配置有通过堆叠多个半导体芯片而获得的多个堆叠的芯片，所述分割的加热器块相对于所述堆叠的芯片形成 以及加热装置，用于选择性地将热传递到经过引线接合的堆叠芯片。

公开(公告)号：US08796076B2

公开(公告)日：2014-08-05

申请号：US13600153

申请日：2012-08-30

申请人： Atsushi Yoshimura ,  Shoko Omizo

发明人： Atsushi Yoshimura ,  Shoko Omizo

IPC分类号： H01L21/00 ,  H01L21/30

CPC分类号： H01L21/6836 ,  H01L21/67132 ,  H01L21/67144 ,  H01L23/3121 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/75745 ,  H01L2224/758 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/181 ,  Y10T156/1744 ,  H01L2924/00014 ,  H01L2924/00012

摘要： After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.

摘要翻译： 通过曝光和显影形成在半导体晶片的电路侧上的感光表面保护膜和粘合剂层形成开口后，通过将单独的芯片切割成具有感光表面保护膜和粘合剂层的半导体芯片， 半导体晶片。 在第二半导体芯片被吸入夹头放置在第一半导体芯片上之后，第二半导体芯片通过第一表面保护膜和粘合剂层与第一半导体芯片接合。 吸入夹头的吸入侧与现在粘接的半导体芯片之间的吸附侧具有比第二半导体芯片更低的粘附力。

公开(公告)号：US08717263B2

公开(公告)日：2014-05-06

申请号：US11783148

申请日：2007-04-06

申请人： Atsushi Yoshimura

发明人： Atsushi Yoshimura

IPC分类号： G09G3/36

CPC分类号： G09G3/36 ,  G06F3/1423 ,  G09G3/001 ,  G09G3/18 ,  G09G2320/02 ,  G09G2320/0233 ,  G09G2320/041 ,  G09G2320/066 ,  G09G2320/0666 ,  G09G2330/028 ,  G09G2370/04

摘要： The present invention is to provide an LCD unit, an LCD apparatus, and a method of setting a drive voltage of the LCD unit with a simple operation. The LCD unit includes a label pasted on a place of the LCD unit, wherein the label includes an information code, which is information-coded from a data of a drive voltage for achieving the best contrast in optical characteristics of the LCD unit. The best drive voltage to drive the LCD unit with the best contrast is thereby easily set.

摘要翻译： 本发明是提供一种LCD单元，LCD装置以及以简单的操作来设定LCD单元的驱动电压的方法。 LCD单元包括粘贴在LCD单元的位置上的标签，其中标签包括从用于实现LCD单元的光学特性的最佳对比度的驱动电压的数据进行信息编码的信息代码。 因此，可以很容易地设置驱动具有最佳对比度的LCD单元的最佳驱动电压。

公开(公告)号：US08629041B2

公开(公告)日：2014-01-14

申请号：US13091682

申请日：2011-04-21

申请人： Yasuo Tane ,  Yukio Katamura ,  Atsushi Yoshimura ,  Fumihiro Iwami ,  Kazuyoshi Sakurai

发明人： Yasuo Tane ,  Yukio Katamura ,  Atsushi Yoshimura ,  Fumihiro Iwami ,  Kazuyoshi Sakurai

IPC分类号： H01L21/00

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/2742 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/279 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83908 ,  H01L2224/85205 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 该方法可以包括通过经由设置在半导体元件的一个表面上的接合层将半导体元件结合到基底构件的第一位置的芯片接合。 该方法可以包括引线接合，通过接合线将形成在半导体元件上的端子连接到形成在基底构件上的端子。 此外，该方法可以包括密封以密封半导体元件和接合线。 接合中的接合层的粘度被控制为不超过密封中的接合层的粘度。

公开(公告)号：US08557635B2

公开(公告)日：2013-10-15

申请号：US13403333

申请日：2012-02-23

申请人： Shoko Omizo ,  Atsushi Yoshimura ,  Fumihiro Iwami

发明人： Shoko Omizo ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC分类号： H01L21/44

CPC分类号： H01L23/52 ,  H01L21/6835 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/83001 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.

摘要翻译： 在一个实施例中，准备具有由第一切割槽分割的多个第一芯片区域的第一半导体晶片，以及设置在多个第一芯片区域的每个电路表面处的第一光敏表面保护和粘合层。 具有由第二切割槽分割的多个第二芯片区域的第二半导体晶片，以及设置在多个第二芯片区域的每个电路表面处的第二光敏表面保护和粘合层通过第二光敏表面保护和粘合剂与第一半导体晶片堆叠 以形成第一芯片区域和第二芯片区域的多个芯片堆叠体。

公开(公告)号：US08276537B2

公开(公告)日：2012-10-02

申请号：US13008443

申请日：2011-01-18

申请人： Yukio Katamura ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

发明人： Yukio Katamura ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC分类号： H01L21/30

CPC分类号： H01L21/6715 ,  H01L21/67109 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L2224/2732 ,  H01L2224/27418 ,  H01L2224/27848 ,  H01L2224/27901 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/743 ,  H01L2224/83191 ,  H01L2224/94 ,  Y10T156/10 ,  H01L2224/27 ,  H01L2924/00

摘要： In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.

摘要翻译： 在一个实施例中，公开了一种用于制造半导体器件的方法。 该方法可以包括在将包含树脂和溶剂的粘合材料附着到与包括晶片的电路图案的第一表面相对的第二表面时，加热粘合材料以蒸发溶剂并降低溶剂的蒸气压 气氛面临着接合材料并加热附着的接合材料以形成接合层。

公开(公告)号：US20120223441A1

公开(公告)日：2012-09-06

申请号：US13403333

申请日：2012-02-23

申请人： Shoko OMIZO ,  Atsushi Yoshimura ,  Fumihiro Iwami

发明人： Shoko OMIZO ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC分类号： H01L23/52 ,  H01L21/50

CPC分类号： H01L23/52 ,  H01L21/6835 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/83001 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.

摘要翻译： 在一个实施例中，准备具有由第一切割槽分割的多个第一芯片区域的第一半导体晶片，以及设置在多个第一芯片区域的每个电路表面处的第一光敏表面保护和粘合层。 具有由第二切割槽分割的多个第二芯片区域的第二半导体晶片，以及设置在多个第二芯片区域的每个电路表面处的第二光敏表面保护和粘合层通过第二光敏表面保护和粘合剂与第一半导体晶片堆叠 以形成第一芯片区域和第二芯片区域的多个芯片堆叠体。

公开(公告)号：US20110281396A1

公开(公告)日：2011-11-17

申请号：US13137097

申请日：2011-07-20

申请人： Atsushi Yoshimura ,  Naoyuki Komuta ,  Hideo Numata

发明人： Atsushi Yoshimura ,  Naoyuki Komuta ,  Hideo Numata

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A stacked electronic component comprises a first electronic component adhered on a substrate via a first adhesive layer, and a second electronic component adhered by using a second adhesive layer thereon. The second adhesive layer has a two-layer structure formed by a same material and having different modulus of elasticity. The second adhesive layer of the two-layer structure has a first layer disposed at the first electronic component side and a second layer disposed at the second electronic component side. The first layer softens or melts at an adhesive temperature. The second layer maintains a layered shape at the adhesive temperature. According to the stacked electronic component, occurrences of an insulation failure and a short circuiting are prevented, and in addition, a peeling failure between the electronic components, an increase of a manufacturing cost, and so on, can be suppressed.