公开(公告)号：US08557635B2

公开(公告)日：2013-10-15

申请号：US13403333

申请日：2012-02-23

申请人： Shoko Omizo ,  Atsushi Yoshimura ,  Fumihiro Iwami

发明人： Shoko Omizo ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC分类号： H01L21/44

CPC分类号： H01L23/52 ,  H01L21/6835 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/83001 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.

摘要翻译： 在一个实施例中，准备具有由第一切割槽分割的多个第一芯片区域的第一半导体晶片，以及设置在多个第一芯片区域的每个电路表面处的第一光敏表面保护和粘合层。 具有由第二切割槽分割的多个第二芯片区域的第二半导体晶片，以及设置在多个第二芯片区域的每个电路表面处的第二光敏表面保护和粘合层通过第二光敏表面保护和粘合剂与第一半导体晶片堆叠 以形成第一芯片区域和第二芯片区域的多个芯片堆叠体。

公开(公告)号：US20120223441A1

公开(公告)日：2012-09-06

申请号：US13403333

申请日：2012-02-23

申请人： Shoko OMIZO ,  Atsushi Yoshimura ,  Fumihiro Iwami

发明人： Shoko OMIZO ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC分类号： H01L23/52 ,  H01L21/50

CPC分类号： H01L23/52 ,  H01L21/6835 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/83001 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： In an embodiment, a first semiconductor wafer having plural first chip areas sectioned by first dicing grooves, and first photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural first chip areas is prepared. A second semiconductor wafer having plural second chip areas sectioned by second dicing grooves, and second photosensitive surface protection and adhesive layers provided at each of circuit surfaces of the plural second chip areas is stacked with the first semiconductor wafer via the second photosensitive surface protection and adhesive layers to form plural chip stacked bodies of the first chip areas and the second chip areas.

摘要翻译： 在一个实施例中，准备具有由第一切割槽分割的多个第一芯片区域的第一半导体晶片，以及设置在多个第一芯片区域的每个电路表面处的第一光敏表面保护和粘合层。 具有由第二切割槽分割的多个第二芯片区域的第二半导体晶片，以及设置在多个第二芯片区域的每个电路表面处的第二光敏表面保护和粘合层通过第二光敏表面保护和粘合剂与第一半导体晶片堆叠 以形成第一芯片区域和第二芯片区域的多个芯片堆叠体。

公开(公告)号：US20130062782A1

公开(公告)日：2013-03-14

申请号：US13600153

申请日：2012-08-30

申请人： Atsushi Yoshimura ,  Shoko Omizo

发明人： Atsushi Yoshimura ,  Shoko Omizo

IPC分类号： H01L23/48 ,  B32B38/18 ,  H01L21/50

CPC分类号： H01L21/6836 ,  H01L21/67132 ,  H01L21/67144 ,  H01L23/3121 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/75745 ,  H01L2224/758 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/181 ,  Y10T156/1744 ,  H01L2924/00014 ,  H01L2924/00012

摘要： After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.

摘要翻译： 通过曝光和显影形成在半导体晶片的电路侧上的感光表面保护膜和粘合剂层形成开口后，通过将单独的芯片切割成具有感光表面保护膜和粘合剂层的半导体芯片， 半导体晶片。 在第二半导体芯片被吸入夹头放置在第一半导体芯片上之后，第二半导体芯片通过第一表面保护膜和粘合剂层与第一半导体芯片接合。 吸入夹头的吸入侧与现在粘接的半导体芯片之间的吸附侧具有比第二半导体芯片更低的粘附力。

公开(公告)号：US08796076B2

公开(公告)日：2014-08-05

申请号：US13600153

申请日：2012-08-30

申请人： Atsushi Yoshimura ,  Shoko Omizo

发明人： Atsushi Yoshimura ,  Shoko Omizo

IPC分类号： H01L21/00 ,  H01L21/30

CPC分类号： H01L21/6836 ,  H01L21/67132 ,  H01L21/67144 ,  H01L23/3121 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/75745 ,  H01L2224/758 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/181 ,  Y10T156/1744 ,  H01L2924/00014 ,  H01L2924/00012

摘要： After formation of an opening by exposing and development of the photosensitive surface protection film and adhesive layer which is formed on the circuit side of the semiconductor wafer, the semiconductor chips having a photosensitive surface protection film and adhesive layer thereon is fabricated by cutting individual chips from the semiconductor wafer. After the second semiconductor chip is placed over the first semiconductor chip up by the suction collet, the second semiconductor chip is bonded with the first semiconductor chip by the first surface protection film and adhesive layer. The suction side of the suction collet has lower adhesion to the second semiconductor chip than that between the now bonded semiconductor chips.

摘要翻译： 通过曝光和显影形成在半导体晶片的电路侧上的感光表面保护膜和粘合剂层形成开口后，通过将单独的芯片切割成具有感光表面保护膜和粘合剂层的半导体芯片， 半导体晶片。 在第二半导体芯片被吸入夹头放置在第一半导体芯片上之后，第二半导体芯片通过第一表面保护膜和粘合剂层与第一半导体芯片接合。 吸入夹头的吸入侧与现在粘接的半导体芯片之间的吸附侧具有比第二半导体芯片更低的粘附力。

公开(公告)号：US07849897B2

公开(公告)日：2010-12-14

申请号：US11892638

申请日：2007-08-24

申请人： Shoko Omizo ,  Atsushi Yoshimura ,  Mitsuhiro Nakao ,  Junya Sagara ,  Masayuki Dohi ,  Tatsuhiko Shirakawa

发明人： Shoko Omizo ,  Atsushi Yoshimura ,  Mitsuhiro Nakao ,  Junya Sagara ,  Masayuki Dohi ,  Tatsuhiko Shirakawa

IPC分类号： B32B41/00

CPC分类号： H01L21/67132 ,  B32B2038/1891 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T156/16

摘要： An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.

摘要翻译： 一种半导体器件的制造装置，包括：夹头; 对准阶段 和送纸机构。 夹头构造成吸附半导体芯片的表面。 该表面位于与结合靶接合的接合面的相反侧。 接合表面设置有膜状粘合剂层。 夹头包括用于加热粘合剂层的加热器。 对准台被配置为支撑半导体芯片并校正半导体芯片的位置。 片材进给机构构造成将释放片材供给到对准台上。

公开(公告)号：US07955896B2

公开(公告)日：2011-06-07

申请号：US12508905

申请日：2009-07-24

申请人： Atsushi Yoshimura ,  Shoko Omizo

发明人： Atsushi Yoshimura ,  Shoko Omizo

IPC分类号： H01L21/00

CPC分类号： H01L23/3107 ,  H01L21/563 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/0541 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/0401

摘要： A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (μ0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (μ0.5 rpm/μ5 rpm) of the viscosity (μ0.5 rpm) at the low-rotation speed to a viscosity (μ5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.

摘要翻译： 第一半导体元件安装在布线板上。 具有突出到第一半导体元件的外周的外侧的部分的第二半导体元件经由粘合剂设置在第一半导体元件上。 粘合剂在10Pa·s至150Pa·s的低转速下具有粘度（μ0.5rpm），以比例（μ0.5rpm/μ5rpm）表示的触变比为2或更高 ）在低转速下的粘度（μ0.5rpm）以高转速进行粘度（μ5rpm）。 第二半导体元件被接合到第一半导体元件上，同时将粘合剂填充在第二半导体元件的突出部分和布线板之间的中空部分中。

公开(公告)号：US20100035381A1

公开(公告)日：2010-02-11

申请号：US12508905

申请日：2009-07-24

申请人： Atsushi Yoshimura ,  Shoko Omizo

发明人： Atsushi Yoshimura ,  Shoko Omizo

IPC分类号： H01L21/50 ,  H01L21/60 ,  H01L21/54

CPC分类号： H01L23/3107 ,  H01L21/563 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/0541 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/0401

摘要： A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (μ0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (μ0.5 rpm/μ5 rpm) of the viscosity (μ0.5 rpm) at the low-rotation speed to a viscosity (μ5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.

摘要翻译： 第一半导体元件安装在布线板上。 具有突出到第一半导体元件的外周的外侧的部分的第二半导体元件经由粘合剂设置在第一半导体元件上。 粘合剂在低转速下的粘度（μ0.5rpm）在10Pa·s至150Pa·s的范围内，触变比为2或更高，以比例（μ0.5rpm/ ）在低转速下的粘度（μ0.5rpm）至高转速下的粘度（μ5rpm）。 第二半导体元件被接合到第一半导体元件上，同时将粘合剂填充在第二半导体元件的突出部分和布线板之间的中空部分中。

公开(公告)号：US20080110546A1

公开(公告)日：2008-05-15

申请号：US11892638

申请日：2007-08-24

申请人： Shoko Omizo ,  Atsushi Yoshimura ,  Mitsuhiro Nakao ,  Junya Sagara ,  Masayuki Dohi ,  Tatsuhiko Shirakawa

发明人： Shoko Omizo ,  Atsushi Yoshimura ,  Mitsuhiro Nakao ,  Junya Sagara ,  Masayuki Dohi ,  Tatsuhiko Shirakawa

IPC分类号： B32B38/10 ,  B32B37/14 ,  B32B38/18 ,  B32B38/00 ,  B32B41/00

CPC分类号： H01L21/67132 ,  B32B2038/1891 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T156/16

摘要： An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.

摘要翻译： 一种半导体器件的制造装置，包括：夹头; 对准阶段 和送纸机构。 夹头构造成吸附半导体芯片的表面。 该表面位于与结合靶接合的接合面的相反侧。 接合表面设置有膜状粘合剂层。 夹头包括用于加热粘合剂层的加热器。 对准台被配置为支撑半导体芯片并校正半导体芯片的位置。 片材进给机构构造成将释放片材供给到对准台上。

公开(公告)号：US06686222B2

公开(公告)日：2004-02-03

申请号：US10147070

申请日：2002-05-17

申请人： Shoko Omizo ,  Atsushi Yoshimura ,  Mikio Matsui ,  Takao Sato

发明人： Shoko Omizo ,  Atsushi Yoshimura ,  Mikio Matsui ,  Takao Sato

IPC分类号： H01L2150

CPC分类号： H01L23/49811 ,  H01L23/544 ,  H01L25/105 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/107 ,  H05K3/4614 ,  H05K3/4638

摘要： In a semiconductor device manufacturing method, a semiconductor element is mounted on a substrate including first connection electrodes, first interconnections electrically connected to the first connection electrodes and a first alignment mark with the semiconductor element electrically connected to the first interconnections. Then, the substrate having the semiconductor element mounted thereon and a core substrate including second connection electrodes and second interconnections electrically connected to the second connection electrode and having adhesive layers formed on both surfaces thereof are positioned with respect to and stacked on each other based on recognition of the first alignment mark, thermo-compression bonding is performed at temperatures at which an adhesive agent of the adhesive layers is melted, without being cured, to temporarily fix the substrate having the semiconductor element mounted thereon on the core substrate by tackiness of the adhesive agent.

摘要翻译： 在半导体器件制造方法中，半导体元件安装在包括第一连接电极的基板上，与第一连接电极电连接的第一互连和与第一互连电连接的半导体元件的第一对准标记。 然后，在其上安装有半导体元件的基板和包括第二连接电极的芯基板和与第二连接电极电连接并且在其两个表面上形成的粘合剂层的第二互连基于识别而相对于彼此定位 在第一对准标记的温度下，在粘合剂层的粘合剂被熔化而不固化的温度下进行热压接，通过粘合剂的粘性将其上安装有半导体元件的基板临时固定在芯基板上 代理商

公开(公告)号：US09006029B2

公开(公告)日：2015-04-14

申请号：US13052144

申请日：2011-03-21

申请人： Yukio Katamura ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

发明人： Yukio Katamura ,  Yasuo Tane ,  Atsushi Yoshimura ,  Fumihiro Iwami

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/27312 ,  H01L2224/27418 ,  H01L2224/27848 ,  H01L2224/29 ,  H01L2224/29011 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法，该半导体器件包括具有形成在第一主表面上的电极焊盘和设置在第二主表面上的接合层的半导体芯片，以及具有安装在该衬底上的半导体芯片的衬底。 制造方法可以包括在基板的前表面上将接合成形材料的半导体芯片的第二主表面的外边缘接触的部分。 该方法可以包括通过接合层将半导体芯片的第二主表面接合到衬底。