-
21.发明授权Semiconductor device, method of manufacturing semiconductor device and communication method 失效半导体器件，半导体器件的制造方法和通信方法公开(公告)号：US06703953B2
公开(公告)日：2004-03-09
申请号：US09457721
申请日：1999-12-10
IPC分类号： H03M166
CPC分类号： H01L23/57 , H01L2223/5444 , H01L2924/0002 , H04M1/67 , H04W12/12 , H01L2924/00
摘要： A channel region (2), a source region (3) and a drain region (4) are formed on a polycrystalline semiconductor layer (1). The characteristic of a polycrystalline TFT (101) is dispersed by the amount of crystal grain boundaries (6) contained in the channel region (2). A drain current is reduced as the amount of the crystal grain boundaries (6) contained in the channel region (2) is increased. In order to utilize a code obtained by encoding the electric characteristic of the TFT (101) for identification of a semiconductor chip, a system or the like, the TFT (101) is mounted on the semiconductor chip, the system or the like along with an encoder circuit. Thus, a barrier against illegal use of a user terminal is improved at a low cost.
摘要翻译： 在多晶半导体层（1）上形成沟道区（2），源区（3）和漏区（4）。 多晶TFT（101）的特性通过包含在沟道区域（2）中的晶粒边界（6）的量而分散。 随着沟道区域（2）中包含的晶界（6）的量增加，漏电流减小。 为了利用通过对用于识别半导体芯片，系统等的TFT（101）的电特性进行编码而获得的代码，TFT（101）安装在半导体芯片，系统等上以及 一个编码器电路。 因此，以低成本提高了防止非法使用用户终端的屏障。
-
公开(公告)号：US06646306B2
公开(公告)日：2003-11-11
申请号：US09985020
申请日：2001-11-01
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
IPC分类号： H01L2701
CPC分类号： H01L21/76286 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/458
摘要： A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.
摘要翻译： 一种防止金属污染的半导体器件以及半导体器件的制造方法。 区域（NR）和区域（PR）由沟槽隔离氧化膜，选择性地设置在沟槽隔离氧化膜上的多晶硅膜，设置在多晶硅膜上的硅层和设置在侧面上的侧壁隔离物 多晶硅膜的表面。 多晶硅膜设置在对应于跨越两个阱区域的SOI层中的P型阱区域和N型阱区域的PN结部分JP的顶部的位置。
-
公开(公告)号：US06586802B2
公开(公告)日：2003-07-01
申请号：US09346726
申请日：1999-07-02
IPC分类号： H01L2701
CPC分类号： H01L27/1203 , H01L29/42384
摘要： A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embedded between the active regions 3 in the silicon layer 3, wherein the insulating layer 2 has spaces 6 positioned in the vicinity of interfaces between the active regions and the element isolating parts 5, whereby it becomes possible to reduce fixed charges or holes existing on a side of the insulating layer in interfaces between the silicon layer and the insulating layer, which fixed charges or holes are generated in a process of oxidation for forming the insulating layer on a bottom surface of the silicon layer.
摘要翻译： 一种半导体器件，包括通过在绝缘层2上形成硅层3，在硅层3中水平布置的多个有源区3和由沟槽状构成的沟槽状形状的元件隔离部5制造的SOI衬底 绝缘体5嵌入在硅层3中的有源区域3之间，其中绝缘层2具有位于有源区域和元件隔离部分5之间的界面附近的空间6，由此可以减少固定电荷或存在的孔 在硅层和绝缘层之间的界面中的绝缘层的一侧上，在硅层的底表面上形成绝缘层的氧化过程中产生固定的电荷或空穴。
-
公开(公告)号：US06335267B1
公开(公告)日：2002-01-01
申请号：US09667498
申请日：2000-09-22
IPC分类号： H01L2120
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.
摘要翻译： 提供半导体衬底和制造半导体器件的方法。 氧化膜（13）通过氧化SOI衬底（10）的边缘部分和下主表面而形成。 通过使用暴露在SOI衬底（10）的边缘部分和下部主表面上的氧化膜（11）作为下面的氧化膜，以类似于LOCOS（硅的局部氧化物）氧化的方式进行该氧化步骤。 然后，氧化膜（13）的厚度大于SOI衬底（10）的边缘部分和下主表面上的氧化物膜（11）的厚度。 半导体衬底防止在其边缘处产生灰尘颗粒。
-
公开(公告)号：US06323527B1
公开(公告)日：2001-11-27
申请号：US09055300
申请日：1998-04-06
申请人： Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L2358
CPC分类号： H01L29/402 , H01L21/28167 , H01L21/28202 , H01L21/28238 , H01L29/513 , H01L29/518 , H01L29/66772 , H01L29/78609
摘要： At an edge portion of an FS gate electrode (10) beneath a side wall oxide film (106), an FS gate oxide film (101) is thicker. Relative to a surface of a silicon substrate (SB) beneath the FS gate oxide film (101), other surface of the silicon substrate (SB) is retracted. Thus, a MOS transistor with field-shield isolation structure and a method for manufacturing the same can be provided with higher reliability of the gate oxide film.
摘要翻译： 在侧壁氧化膜（106）下面的FS栅极（10）的边缘部分，FS栅极氧化膜（101）较厚。 相对于FS栅极氧化膜（101）下面的硅衬底（SB）的表面，硅衬底（SB）的另一表面缩回。 因此，具有场屏蔽隔离结构的MOS晶体管及其制造方法可以提供更高的栅极氧化膜的可靠性。
-
公开(公告)号：US06271065B1
公开(公告)日：2001-08-07
申请号：US09494352
申请日：2000-01-31
申请人： Shoichi Miyamoto , Takashi Ipposhi
发明人： Shoichi Miyamoto , Takashi Ipposhi
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78636
摘要： On an insulating film a mesa-isolation silicon layer is formed, in which a channel region and source/drain regions ar included. A gate insulating film and a conducting layer as a part of a gate electrode are stacked on the mesa-isolation silicon layer. A sidewall of an insulating material is formed on side surfaces of the mesa-isolation silicon layer, gate insulating film, and conducting layer at an end portion of the channel region of the mesa-isolation silicon layer, and a gate electrode is formed on the conducting layer.
摘要翻译： 在绝缘膜上形成台状隔离硅层，其中包括沟道区和源极/漏极区。 栅极绝缘膜和作为栅电极的一部分的导电层堆叠在台面隔离硅层上。 在台面隔离硅层的沟道区的端部的台面隔离硅层，栅极绝缘膜和导电层的侧面形成绝缘材料的侧壁，在 导电层。
-
公开(公告)号：US06171889B2
公开(公告)日：2001-01-09
申请号：US09179897
申请日：1998-10-28
申请人： Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/26506 , H01L21/84 , H01L27/1203
摘要： This invention provides a semiconductor device with a SOI structure and a method of manufacturing the same, preventing deterioration in and making improvement in device characteristics. Nitrogen ion implantation into NMOS and PMOS regions (NR, PR) with resists (22b) and (22c) as masks, respectively, introduces nitrogen ions into channel doped layers (31). The subsequent thermal treatment provides a structure with the channel doped layers (31) containing nitrogen having a prescribed concentration distribution in the depth direction.
摘要翻译： 本发明提供具有SOI结构的半导体器件及其制造方法，防止器件特性的劣化和改善。 分别以抗蚀剂（22b）和（22c）作为掩模的氮离子注入到NMOS和PMOS区域（NR，PR）中，将氮离子引入沟道掺杂层（31）。 随后的热处理提供了在深度方向上含有具有规定浓度分布的氮的沟道掺杂层（31）的结构。
-
公开(公告)号：US6150696A
公开(公告)日：2000-11-21
申请号：US55903
申请日：1998-04-07
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor substrate and a method of fabricating a semiconductor device are provided. An oxide film (13) is formed by oxidizing an edge section and a lower major surface of an SOI substrate (10). This oxidizing step is performed in a manner similar to LOCOS (Local Oxide of Silicon) oxidation by using an oxide film (11) exposed on the edge section and lower major surface of the SOI substrate (10) as an underlying oxide film. Then, the thickness of the oxide film (13) is greater than that of the oxide film (11) on the edge section and lower major surface of the SOI substrate (10). The semiconductor substrate prevents particles of dust from being produced at the edge thereof.
-
公开(公告)号：US5910672A
公开(公告)日：1999-06-08
申请号：US888898
申请日：1997-07-07
申请人： Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L21/265 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/76
CPC分类号： H01L29/66772 , H01L21/26506 , H01L21/84 , H01L27/1203
摘要： This invention provides a semiconductor device with a SOI structure and a method of manufacturing the same, preventing deterioration in and making improvement in device characteristics. Nitrogen ion implantation into NMOS and PMOS regions (NR, PR) with resists (22b) and (22c) as masks, respectively, introduces nitrogen ions into channel doped layers (31). The subsequent thermal treatment provides a structure with the channel doped layers (31) containing nitrogen having a prescribed concentration distribution in the depth direction.
摘要翻译： 本发明提供具有SOI结构的半导体器件及其制造方法，防止器件特性的劣化和改善。 分别以抗蚀剂（22b）和（22c）作为掩模的氮离子注入到NMOS和PMOS区域（NR，PR）中，将氮离子引入沟道掺杂层（31）。 随后的热处理提供了在深度方向上含有具有规定浓度分布的氮的沟道掺杂层（31）的结构。
-
30.发明授权Three-dimensional shape measuring device and three-dimensional shape measuring sensor 失效三维形状测量装置和三维形状测量传感器
公开(公告)号：US5381235A
公开(公告)日：1995-01-10
申请号：US990460
申请日：1992-12-15
CPC分类号： G01B11/024 , G01B11/2518
摘要： The present invention provides a three-dimensional shape measuring device and a sensor employed for the three-dimensional shape measuring device. The three-dimensional shape measuring device comprises a light source for scanning plane light over the surface of an object, an image sensor opposed to the object and provided with a plurality of pixels, an optical system for forming an image of a bright line appearing on the surface of the object due to plane light on the image sensor, a plurality of capacitors installed in association with pixels of the image sensor, a charger for storing given charges in a plurality of capacitors before plane light scanning starts, a plurality of dischargers lying in association with capacitors and gradually discharging the capacitors for pixels corresponding to a bright line image from when plane light scanning starts until the bright line image passes through the pixels, and an arithmetic logic means for computing charges remaining in the plurality of capacitors after plane light scanning is completed and thus providing a three-dimensional shape of an object. Thereby, a three-dimensional shape of an object can be measured at a high speed with high precision.
摘要翻译： 本发明提供了三维形状测量装置和用于三维形状测量装置的传感器。 三维形状测量装置包括：用于扫描物体表面上的平面光的光源，与该物体相对并设置有多个像素的图像传感器，用于形成亮线的图像的光学系统， 由于图像传感器上的平面光，物体的表面，与图像传感器的像素相关联地安装的多个电容器，用于在平面光扫描开始之前在多个电容器中存储给定电荷的充电器，多个放电器位于 与平面光扫描开始直到亮线图像通过像素的与亮线图像相对应的像素的电容器逐渐放电;以及算术逻辑装置，用于计算平面光后的多个电容器中剩余的电荷 扫描完成，从而提供对象的三维形状。 由此，可以高精度地测量物体的三维形状。
-
-
-
-
-
-
-
-
-
搜索结果
156 条记录 (耗时 0.028 秒)
