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188 条记录 (耗时 0.022 秒)

    MRAM with sidewall protection and method of fabrication
    21.
    发明申请
    MRAM with sidewall protection and method of fabrication 有权
    MRAM具有侧壁保护和制造方法

    公开(公告)号：US20130032775A1

    公开(公告)日：2013-02-07

    申请号：US13317564

    申请日：2011-10-20

    申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

    发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Ebrahim Abedifard

    IPC分类号： H01L45/00

    CPC分类号： H01L23/5226 ,  H01L27/222 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

    摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

    摘要翻译： 描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。 一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。 层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。 选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。 第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。

    MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F² MEMORY CELLS
    22.
    发明申请
    MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F² MEMORY CELLS 有权
    具有4个F²存储单元的连续阵列的存储器件

    公开(公告)号：US20140138600A1

    公开(公告)日：2014-05-22

    申请号：US13680037

    申请日：2012-11-17

    申请人： Kimihiro SATOH ,  Yiming Huai

    发明人： Kimihiro SATOH ,  Yiming Huai

    IPC分类号： H01L45/00 ,  H01L27/088

    CPC分类号： H01L45/1233 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    摘要： A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

    摘要翻译： 存储器件包括其中具有多个平行沟槽的半导体衬底，形成在衬底中的存储区包括存储单元阵列，存储单元阵列具有形成在沟槽侧壁中的各个沟道的多个垂直选择晶体管，多个埋入源电​​极 沟槽底部，形成在一对沟槽侧壁上的多个成对栅极电极，分别沿着包括第一和第二排栅极触点的沟槽方向邻近存储区域设置的第一和第二缝合区域，以及一排源极触点， 第一或第二针脚区域，其中每个源极触点耦合到相应的一个源极电极。 每对栅电极中的一个耦合到第一行栅极触点中的相应一个，并且每对栅电极中的另一个耦合到第二行栅极触点的相应一个。

    Magnetic random access memory with field compensating layer and multi-level cell
    25.
    发明授权
    Magnetic random access memory with field compensating layer and multi-level cell 有权
    具有场补偿层和多级单元的磁随机存取存储器

    公开(公告)号：US08565010B2

    公开(公告)日：2013-10-22

    申请号：US13099321

    申请日：2011-05-02

    申请人： Yuchen Zhou ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Jing Zhang

    发明人： Yuchen Zhou ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Jing Zhang

    IPC分类号： G11C11/15

    CPC分类号： G11C11/16 ,  G11C11/161 ,  H01L43/02

    摘要： A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.

    摘要翻译： 自旋转矩磁性随机存取存储器（STTMRAM）元件包括形成在基板上的参考层，具有固定的垂直磁性分量。 接合层形成在参考层的顶部，并且在接合层的顶部上以自由层的大致中心位置处具有垂直磁性取向形成自由层。 间隔层形成在自由层的顶部，固定层形成在间隔层的顶部，固定层具有与基准层相反的固定的垂直磁性部件。 自由层的磁性取向相对于固定层的磁性取向。 固定层和参考层的垂直磁性分量基本相互抵消，自由层具有面内边缘磁化场。

    Magnetic random access memory with switching assist layer
    26.
    发明授权
    Magnetic random access memory with switching assist layer 有权
    具有开关辅助层的磁性随机存取存储器

    公开(公告)号：US08492860B2

    公开(公告)日：2013-07-23

    申请号：US13289372

    申请日：2011-11-04

    申请人： Yuchen Zhou ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Roger Klas Malmhall

    发明人： Yuchen Zhou ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Roger Klas Malmhall

    IPC分类号： H01L29/82

    CPC分类号： H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01L43/08 ,  H01L43/10

    摘要： A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer.

    摘要翻译： STTMRAM元件包括由非磁性分离层（NMSL）隔开的由第一自由层和第二自由层制成的磁化层，第一和第二自由层各自具有彼此作用的面内磁化 反平行耦合。 在向STTMRAM元件施加电流之前，第一自由层和第二自由层的磁化方向各自在同一平面内，此后，第二自由层的磁化方向基本上标称为平面外，并且 第一自由层开关的磁化方向。 当电流停止到STTMRAM元件时，第二自由层的磁化方向保持在与第一自由层基本相反的方向上。

    Method for Bit-Error Rate Testing of Resistance-based RAM Cells Using a Reflected Signal
    27.
    发明申请
    Method for Bit-Error Rate Testing of Resistance-based RAM Cells Using a Reflected Signal 有权
    使用反射信号的基于电阻的RAM单元的误码率测试方法

    公开(公告)号：US20130294144A1

    公开(公告)日：2013-11-07

    申请号：US13462708

    申请日：2012-05-02

    申请人： Zihui Wang ,  Yuchen Zhou ,  Jing Zhang ,  Yiming Huai

    发明人： Zihui Wang ,  Yuchen Zhou ,  Jing Zhang ,  Yiming Huai

    IPC分类号： G11C11/00

    CPC分类号： G11C29/50008 ,  G11C11/16 ,  G11C13/00 ,  G11C29/08 ,  G11C29/44 ,  G11C29/50 ,  G11C29/56008 ,  G11C29/56016 ,  G11C2029/5602

    摘要： A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external contact pads (or points) on the surface of the wafer (or chip). In the test setup the memory cell is connected an impedance mismatched transmission line through a probe for un-buffered, fast switching of the cell between the high and low resistance states without the need for CMOS logic to select and drive the cell. The unbalanced transmission line is used generate signal reflections from the cell that are a function of the resistance state. The reflected signal is used to detect whether the test cell has switched as expected.

    摘要翻译： 描述了一种测试方法，用于在晶片或芯片级上对基于电阻的RAM单元（如MTJ单元）执行快速误码率（BER）测量。 实施例使用一个或多个专门设计的测试存储单元，该测试存储单元通过电池的两个电极和晶片（或芯片）表面上的外部接触垫（或点）之间的直接电连接制造。 在测试设置中，存储单元通过探头连接阻抗不匹配的传输线，用于高电阻和低电阻状态之间的单元的非缓冲，快速切换，而不需要CMOS逻辑来选择和驱动单元。 使用不平衡传输线从电池产生作为电阻状态的函数的信号反射。 反射信号用于检测测试单元是否按预期切换。

    Method for forming a hard bias structure in a magnetoresistive sensor
    28.
    发明授权
    Method for forming a hard bias structure in a magnetoresistive sensor 失效
    在磁阻传感器中形成硬偏压结构的方法

    公开(公告)号：US07284316B1

    公开(公告)日：2007-10-23

    申请号：US10991712

    申请日：2004-11-17

    申请人： Yiming Huai ,  Jinqiu Zhang ,  Jing Zhang

    发明人： Yiming Huai ,  Jinqiu Zhang ,  Jing Zhang

    IPC分类号： G11B5/127 ,  H04R31/00

    CPC分类号： G11B5/3932 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3163 ,  G11B2005/3996 ,  Y10T29/49034 ,  Y10T29/49043 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

    摘要： A method for forming a hard bias structure in a magnetoresistive sensor is disclosed. A magnetoresistive sensor having a soft magnetic bias layer, spacer layer, and a magnetoresistive layer, is formed over a substrate having a gap layer. A mask is formed over a portion of the magnetoresistive sensor structure to define a central region. The masked structure is ion milled to remove portions not shielded by the mask, to form the central region with sloped sides, and to expose a region of the gap layer laterally adjacent the sloped sides. A first underlayer is deposited onto at least the sloped sides at a high deposition angle. A second underlayer is deposited to at least partially overlap the first underlayer, and at a first lower deposition angle. A hard bias layer is deposited over at least a portion of the second underlayer, and at a second lower deposition angle.

    摘要翻译： 公开了一种在磁阻传感器中形成硬偏压结构的方法。 在具有间隙层的衬底上形成具有软磁偏置层，间隔层和磁阻层的磁阻传感器。 在磁阻传感器结构的一部分上形成掩模以限定中心区域。 被掩蔽的结构被离子研磨以去除未被掩模屏蔽的部分，以形成具有倾斜侧面的中心区域，并且使间隙层的区域横向暴露在倾斜侧面附近。 第一底层以高沉积角度沉积在至少倾斜的侧面上。 沉积第二底层至少部分地与第一底层重叠，并且以第一较低沉积角度沉积。 硬偏压层沉积在第二底层的至少一部分上，并且沉积在第二较低沉积角度。

    Magnetoresistive sensor with overlapping leads having distributed current
    29.
    发明授权
    Magnetoresistive sensor with overlapping leads having distributed current 有权
    具有重叠引线的磁阻传感器具有分布电流

    公开(公告)号：US06989972B1

    公开(公告)日：2006-01-24

    申请号：US10261119

    申请日：2002-09-30

    申请人： Kroum Stoev ,  Mathew Gibbons ,  Francis Liu ,  Bogdan M. Simion ,  Aparna C. Vadde ,  Jing Zhang ,  Yiming Huai ,  Marcos M. Lederman

    发明人： Kroum Stoev ,  Mathew Gibbons ,  Francis Liu ,  Bogdan M. Simion ,  Aparna C. Vadde ,  Jing Zhang ,  Yiming Huai ,  Marcos M. Lederman

    IPC分类号： G11B5/39

    CPC分类号： G11B5/3932

    摘要： Magnetoresistive (MR) sensors have leads that overlap a MR structure and distribute current to the MR structure so that the current is not concentrated in small portions of the leads. An electrically resistive capping layer can be formed between the leads and the MR structure to distribute the current. The leads can include resistive layers and conductive layers, the resistive layers having a thickness-to-resistivity ratio that is greater than that of each of the conductive layers. The resistive layers may protect the conductive layers during MR structure etching, so that the leads have broad layers of electrically conductive material for connection to MR structures. The broad leads conduct heat better than the read gap material that they replace, further reducing the temperature at the connection between the leads and the MR structure.

    摘要翻译： 磁阻（MR）传感器具有与MR结构重叠并且将电流分配到MR结构的引线，使得电流不集中在引线的小部分中。 可以在引线和MR结构之间形成电阻覆盖层以分布电流。 引线可以包括电阻层和导电层，电阻层的厚度 - 电阻率比大于每个导电层的厚度 - 电阻率比。 电阻层可以在MR结构蚀刻期间保护导电层，使得引线具有用于连接到MR结构的宽的导电材料层。 宽引线比它们所替代的读取间隙材料更好地传导热量，进一步降低引线与MR结构之间的连接处的温度。

    Magnetoresistive sensor with overlapping lead layers including alpha tantalum and conductive layers
    30.
    发明授权
    Magnetoresistive sensor with overlapping lead layers including alpha tantalum and conductive layers 失效
    具有重叠引线层的磁阻传感器，包括α钽和导电层

    公开(公告)号：US06934129B1

    公开(公告)日：2005-08-23

    申请号：US10260896

    申请日：2002-09-30

    申请人： Jinqiu Zhang ,  Jing Zhang ,  Yiming Huai ,  Lifan Chen

    发明人： Jinqiu Zhang ,  Jing Zhang ,  Yiming Huai ,  Lifan Chen

    IPC分类号： G11B5/39

    CPC分类号： G11B5/3932

    摘要： Magnetoresistive (MR) sensors are disclosed that have leads that overlap a MR structure and distribute current to and from the MR structure so that the current is not concentrated in small portions of the leads, alleviating the problems mentioned above. For example, the leads can be formed of a body-centered cubic (bcc) form of tantalum, combined with gold or other highly conductive materials. For the situation in which a thicker bcc tantalum layer covers a highly conductive gold layer, the tantalum layer protects the gold layer during MR structure etching, so that the leads can have broad layers of electrically conductive material for connection to MR structures. The broad leads also conduct heat better than the read gap material that they replace, further reducing the temperature at the connection between the leads and the MR structure.

    摘要翻译： 公开了磁阻（MR）传感器，其具有与MR结构重叠的引线并且将电流分配到MR结构和从MR结构分配电流，使得电流不集中在引线的小部分中，减轻了上述问题。 例如，引线可以由体心立方（bcc）形式的钽形成，与金或其它高导​​电材料组合。 对于较厚的bcc钽层覆盖高导电金层的情况，钽层在MR结构蚀刻期间保护金层，使得引线可以具有用于连接到MR结构的宽层导电材料。 宽引线还比它们所替代的读取间隙材料更好地传导热量，进一步降低引线与MR结构之间的连接处的温度。