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369 条记录 (耗时 0.038 秒)

    Method for forming a hard bias structure in a magnetoresistive sensor
    1.
    发明授权
    Method for forming a hard bias structure in a magnetoresistive sensor 失效
    在磁阻传感器中形成硬偏压结构的方法

    公开(公告)号：US07284316B1

    公开(公告)日：2007-10-23

    申请号：US10991712

    申请日：2004-11-17

    申请人： Yiming Huai ,  Jinqiu Zhang ,  Jing Zhang

    发明人： Yiming Huai ,  Jinqiu Zhang ,  Jing Zhang

    IPC分类号： G11B5/127 ,  H04R31/00

    CPC分类号： G11B5/3932 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3163 ,  G11B2005/3996 ,  Y10T29/49034 ,  Y10T29/49043 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

    摘要： A method for forming a hard bias structure in a magnetoresistive sensor is disclosed. A magnetoresistive sensor having a soft magnetic bias layer, spacer layer, and a magnetoresistive layer, is formed over a substrate having a gap layer. A mask is formed over a portion of the magnetoresistive sensor structure to define a central region. The masked structure is ion milled to remove portions not shielded by the mask, to form the central region with sloped sides, and to expose a region of the gap layer laterally adjacent the sloped sides. A first underlayer is deposited onto at least the sloped sides at a high deposition angle. A second underlayer is deposited to at least partially overlap the first underlayer, and at a first lower deposition angle. A hard bias layer is deposited over at least a portion of the second underlayer, and at a second lower deposition angle.

    摘要翻译： 公开了一种在磁阻传感器中形成硬偏压结构的方法。 在具有间隙层的衬底上形成具有软磁偏置层，间隔层和磁阻层的磁阻传感器。 在磁阻传感器结构的一部分上形成掩模以限定中心区域。 被掩蔽的结构被离子研磨以去除未被掩模屏蔽的部分，以形成具有倾斜侧面的中心区域，并且使间隙层的区域横向暴露在倾斜侧面附近。 第一底层以高沉积角度沉积在至少倾斜的侧面上。 沉积第二底层至少部分地与第一底层重叠，并且以第一较低沉积角度沉积。 硬偏压层沉积在第二底层的至少一部分上，并且沉积在第二较低沉积角度。

    Magnetoresistive sensor with overlapping lead layers including alpha tantalum and conductive layers
    2.
    发明授权
    Magnetoresistive sensor with overlapping lead layers including alpha tantalum and conductive layers 失效
    具有重叠引线层的磁阻传感器，包括α钽和导电层

    公开(公告)号：US06934129B1

    公开(公告)日：2005-08-23

    申请号：US10260896

    申请日：2002-09-30

    申请人： Jinqiu Zhang ,  Jing Zhang ,  Yiming Huai ,  Lifan Chen

    发明人： Jinqiu Zhang ,  Jing Zhang ,  Yiming Huai ,  Lifan Chen

    IPC分类号： G11B5/39

    CPC分类号： G11B5/3932

    摘要： Magnetoresistive (MR) sensors are disclosed that have leads that overlap a MR structure and distribute current to and from the MR structure so that the current is not concentrated in small portions of the leads, alleviating the problems mentioned above. For example, the leads can be formed of a body-centered cubic (bcc) form of tantalum, combined with gold or other highly conductive materials. For the situation in which a thicker bcc tantalum layer covers a highly conductive gold layer, the tantalum layer protects the gold layer during MR structure etching, so that the leads can have broad layers of electrically conductive material for connection to MR structures. The broad leads also conduct heat better than the read gap material that they replace, further reducing the temperature at the connection between the leads and the MR structure.

    摘要翻译： 公开了磁阻（MR）传感器，其具有与MR结构重叠的引线并且将电流分配到MR结构和从MR结构分配电流，使得电流不集中在引线的小部分中，减轻了上述问题。 例如，引线可以由体心立方（bcc）形式的钽形成，与金或其它高导​​电材料组合。 对于较厚的bcc钽层覆盖高导电金层的情况，钽层在MR结构蚀刻期间保护金层，使得引线可以具有用于连接到MR结构的宽层导电材料。 宽引线还比它们所替代的读取间隙材料更好地传导热量，进一步降低引线与MR结构之间的连接处的温度。

    Memory device including transistor array with shared plate channel and method for making the same
    5.
    发明授权
    Memory device including transistor array with shared plate channel and method for making the same 有权
    存储器件包括具有共享板通道的晶体管阵列及其制造方法

    公开(公告)号：US08704206B2

    公开(公告)日：2014-04-22

    申请号：US13356633

    申请日：2012-01-23

    申请人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

    发明人： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang

    IPC分类号： H01L29/06 ,  H01L47/00 ,  H01L29/78 ,  H01L21/336

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    摘要： The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

    摘要翻译： 本发明涉及其中结合有新颖的存储单元架构的存储器件，其包括共享公共通道的选择晶体管阵列及其制造方法。 存储器件包括具有第一类型导电性的半导体衬底，多个漏极区域和由衬底中的公共板沟道分开的公共源极区域，以及选择栅极，其设置在板沟道的顶部，栅极介电层插入 之间。 多个漏极区域和公共源极区域具有与设置在衬底中的第一类型相反的第二类型导电性。

    Magnetic random access memory with field compensating layer and multi-level cell
    6.
    发明授权
    Magnetic random access memory with field compensating layer and multi-level cell 有权
    具有场补偿层和多级单元的磁随机存取存储器

    公开(公告)号：US08565010B2

    公开(公告)日：2013-10-22

    申请号：US13099321

    申请日：2011-05-02

    申请人： Yuchen Zhou ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Jing Zhang

    发明人： Yuchen Zhou ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Jing Zhang

    IPC分类号： G11C11/15

    CPC分类号： G11C11/16 ,  G11C11/161 ,  H01L43/02

    摘要： A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.

    摘要翻译： 自旋转矩磁性随机存取存储器（STTMRAM）元件包括形成在基板上的参考层，具有固定的垂直磁性分量。 接合层形成在参考层的顶部，并且在接合层的顶部上以自由层的大致中心位置处具有垂直磁性取向形成自由层。 间隔层形成在自由层的顶部，固定层形成在间隔层的顶部，固定层具有与基准层相反的固定的垂直磁性部件。 自由层的磁性取向相对于固定层的磁性取向。 固定层和参考层的垂直磁性分量基本相互抵消，自由层具有面内边缘磁化场。

    Magnetic random access memory with switching assist layer
    7.
    发明授权
    Magnetic random access memory with switching assist layer 有权
    具有开关辅助层的磁性随机存取存储器

    公开(公告)号：US08492860B2

    公开(公告)日：2013-07-23

    申请号：US13289372

    申请日：2011-11-04

    申请人： Yuchen Zhou ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Roger Klas Malmhall

    发明人： Yuchen Zhou ,  Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Roger Klas Malmhall

    IPC分类号： H01L29/82

    CPC分类号： H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01L43/08 ,  H01L43/10

    摘要： A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer.

    摘要翻译： STTMRAM元件包括由非磁性分离层（NMSL）隔开的由第一自由层和第二自由层制成的磁化层，第一和第二自由层各自具有彼此作用的面内磁化 反平行耦合。 在向STTMRAM元件施加电流之前，第一自由层和第二自由层的磁化方向各自在同一平面内，此后，第二自由层的磁化方向基本上标称为平面外，并且 第一自由层开关的磁化方向。 当电流停止到STTMRAM元件时，第二自由层的磁化方向保持在与第一自由层基本相反的方向上。

    Trough channel transistor and methods for making the same
    8.
    发明申请
    Trough channel transistor and methods for making the same 审中-公开
    槽通道晶体管及其制作方法

    公开(公告)号：US20120306005A1

    公开(公告)日：2012-12-06

    申请号：US13136051

    申请日：2011-07-21

    申请人： Kimihiro Satoh ,  Jing Zhang ,  Yiming Huai

    发明人： Kimihiro Satoh ,  Jing Zhang ,  Yiming Huai

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/7851

    摘要： The present invention relates to transistor devices having a trough channel structure through which electrical current flows and methods for making the same. A transistor device having a semiconductor trough structure comprises a semiconductor substrate of a first conductivity type having a top surface; a semiconductor trough protruded from the top surface of the substrate along a first direction and having two top surfaces, two outer lateral surfaces, and an inner surface; a layer of isolation insulator disposed on the substrate and abutting the outer lateral surfaces of the semiconductor trough; a gate dielectric layer lining the inner surface and the top surfaces of the semiconductor trough; and a gate electrode disposed on top of the isolation insulator and extending over and filling the semiconductor trough with the gate dielectric layer interposed therebetween. The gate electrode extends along a second direction not parallel to the first direction provided in the semiconductor trough. Regions of the semiconductor trough not directly beneath the gate electrode have a second conductivity type opposite to the first conductivity type provided in the substrate.

    摘要翻译： 本发明涉及具有通过电流流过的槽槽结构的晶体管器件及其制造方法。 具有半导体槽结构的晶体管器件包括具有顶表面的第一导电类型的半导体衬底; 半导体槽沿着第一方向从基板的顶表面突出并具有两个顶表面，两个外侧表面和内表面; 隔离绝缘层，设置在所述基板上并邻接所述半导体槽的外侧表面; 栅极电介质层，衬在半导体槽的内表面和顶表面上; 以及栅电极，其设置在隔离绝缘体的顶部并且延伸并填充半导体槽，栅介电层插入其间。 栅电极沿着不平行于半导体槽中的第一方向的第二方向延伸。 不直接在栅电极下方的半导体槽的区域具有与设置在基板中的第一导电类型相反的第二导电类型。

    MTJ MRAM WITH STUD PATTERNING
    9.
    发明申请
    MTJ MRAM WITH STUD PATTERNING 有权
    MTJ MRAM与STUD PATTERNING

    公开(公告)号：US20140042567A1

    公开(公告)日：2014-02-13

    申请号：US13572197

    申请日：2012-08-10

    申请人： Dong Ha Jung ,  Kimihiro Satoh ,  Jing Zhang ,  Yuchen Zhou ,  Yiming Huai

    发明人： Dong Ha Jung ,  Kimihiro Satoh ,  Jing Zhang ,  Yuchen Zhou ,  Yiming Huai

    IPC分类号： H01L43/12 ,  H01L43/02

    CPC分类号： H01L43/12 ,  H01L43/08

    摘要： Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase.

    摘要翻译： 描述了包括螺柱掩模和用于MTJ蚀刻以形成比MTJ柱的其余部分宽的底部电极的可移除间隔套的多层蚀刻掩模的使用。 所描述的本发明的第一实施例包括顶部电极和螺柱掩模。 在第二和第三实施例中，螺柱掩模是导电材料，并且还用作顶部电极。 在形成螺柱掩模之后的实施例中，在其周围形成间隔套，以最初增加蚀刻阶段的掩模宽度。 去除间隔物用于进一步蚀刻，以产生逐渐转移到形成MTJ柱的层中的阶梯结构。 在一个实施例中，间隔套筒是在蚀刻阶段期间通过净聚合物沉积形成的。

    Method for Bit-Error Rate Testing of Resistance-based RAM Cells Using a Reflected Signal
    10.
    发明申请
    Method for Bit-Error Rate Testing of Resistance-based RAM Cells Using a Reflected Signal 有权
    使用反射信号的基于电阻的RAM单元的误码率测试方法

    公开(公告)号：US20130294144A1

    公开(公告)日：2013-11-07

    申请号：US13462708

    申请日：2012-05-02

    申请人： Zihui Wang ,  Yuchen Zhou ,  Jing Zhang ,  Yiming Huai

    发明人： Zihui Wang ,  Yuchen Zhou ,  Jing Zhang ,  Yiming Huai

    IPC分类号： G11C11/00

    CPC分类号： G11C29/50008 ,  G11C11/16 ,  G11C13/00 ,  G11C29/08 ,  G11C29/44 ,  G11C29/50 ,  G11C29/56008 ,  G11C29/56016 ,  G11C2029/5602

    摘要： A testing method is described for performing a fast bit-error rate (BER) measurement on resistance-based RAM cells, such MTJ cells, at the wafer or chip level. Embodiments use one or more specially designed test memory cells fabricated with direct electrical connections between the two electrodes of the cell and external contact pads (or points) on the surface of the wafer (or chip). In the test setup the memory cell is connected an impedance mismatched transmission line through a probe for un-buffered, fast switching of the cell between the high and low resistance states without the need for CMOS logic to select and drive the cell. The unbalanced transmission line is used generate signal reflections from the cell that are a function of the resistance state. The reflected signal is used to detect whether the test cell has switched as expected.

    摘要翻译： 描述了一种测试方法，用于在晶片或芯片级上对基于电阻的RAM单元（如MTJ单元）执行快速误码率（BER）测量。 实施例使用一个或多个专门设计的测试存储单元，该测试存储单元通过电池的两个电极和晶片（或芯片）表面上的外部接触垫（或点）之间的直接电连接制造。 在测试设置中，存储单元通过探头连接阻抗不匹配的传输线，用于高电阻和低电阻状态之间的单元的非缓冲，快速切换，而不需要CMOS逻辑来选择和驱动单元。 使用不平衡传输线从电池产生作为电阻状态的函数的信号反射。 反射信号用于检测测试单元是否按预期切换。