公开(公告)号：US11545223B2

公开(公告)日：2023-01-03

申请号：US17117937

申请日：2020-12-10

Applicant: Kioxia Corporation

Inventor： Kenji Sakurada ,  Naomi Takeda ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06 ,  G11C16/34 ,  H01L27/115

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

公开(公告)号：US11437096B2

公开(公告)日：2022-09-06

申请号：US17005443

申请日：2020-08-28

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C11/00 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  H01L27/11582 ,  G11C16/30 ,  H01L27/1157 ,  G11C16/08

Abstract: According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.

公开(公告)号：US11347584B2

公开(公告)日：2022-05-31

申请号：US16807220

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Masanobu Shirakawa ,  Hideki Yamada ,  Marie Takada ,  Ryo Yamaki ,  Osamu Torii ,  Naomi Takeda

IPC: G06F11/10 ,  G06F13/28 ,  G06F11/30 ,  G06F11/16 ,  G06F3/06 ,  G06F9/30

Abstract: A memory system controls a shift register memory and writes encoded data including a plurality of error correction code frames into a block of the shift register memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

公开(公告)号：US11238936B2

公开(公告)日：2022-02-01

申请号：US17014677

申请日：2020-09-08

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Marie Takada ,  Tsukasa Tokutomi ,  Yoshihisa Kojima ,  Kiichi Tachi

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L27/1157 ,  G11C16/12 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/10

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

公开(公告)号：US11237763B2

公开(公告)日：2022-02-01

申请号：US16816439

申请日：2020-03-12

Applicant: Kioxia Corporation

Inventor： Yoshihiro Ueda ,  Naomi Takeda ,  Masanobu Shirakawa ,  Marie Takada

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/10

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of storage blocks, each including a shift register. The control circuit controls writing and reading of data to and from the nonvolatile memory. The control circuit is configured to: read target data from a first storage block of the plurality of storage blocks; and write the target data read from the first storage block to a second storage block of the plurality of storage blocks, the second storage block being different from the first storage block.

公开(公告)号：US12094541B2

公开(公告)日：2024-09-17

申请号：US17452463

申请日：2021-10-27

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Kengo Kurose ,  Marie Takada ,  Ryo Yamaki ,  Kiyotaka Iwasaki ,  Yoshihisa Kojima

IPC: G11C7/00 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C29/52 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/5671 ,  G11C16/0483 ,  G11C29/52 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

公开(公告)号：US12027203B2

公开(公告)日：2024-07-02

申请号：US18321338

申请日：2023-05-22

Applicant: KIOXIA CORPORATION

Inventor： Tomonori Takahashi ,  Masanobu Shirakawa ,  Osamu Torii ,  Marie Takada

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

公开(公告)号：US11776651B2

公开(公告)日：2023-10-03

申请号：US17202432

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Masanobu Shirakawa ,  Hideki Yamada ,  Marie Takada

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/20 ,  G11C29/12 ,  G11C29/18

CPC classification number: G11C29/42 ,  G11C29/12005 ,  G11C29/20 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.

公开(公告)号：US11742026B2

公开(公告)日：2023-08-29

申请号：US17869081

申请日：2022-07-20

Applicant: KIOXIA CORPORATION

Inventor： Hideki Yamada ,  Marie Takada ,  Masanobu Shirakawa

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/10 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C11/5628

Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

公开(公告)号：US11514986B2

公开(公告)日：2022-11-29

申请号：US17202627

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Kengo Kurose ,  Masanobu Shirakawa ,  Hideki Yamada ,  Marie Takada

IPC: G11C16/04 ,  G11C16/16 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11556

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.