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    Flash memory cell with split gate structure and method for forming the same
    23.
    发明授权
    Flash memory cell with split gate structure and method for forming the same 有权
    具有分离栅结构的闪存单元及其形成方法

    公开(公告)号：US07951670B2

    公开(公告)日：2011-05-31

    申请号：US11368714

    申请日：2006-03-06

    申请人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

    发明人： Chen-Ming Huang ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chang-Jen Hsieh ,  Ya-Chen Kao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    摘要： A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.

    摘要翻译： 分离门存储单元。 浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。 浮栅设置在一对隔离结构之间，并且不与其上表面重叠。 盖层设置在浮动栅上。 控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。 源极区域形成在靠近浮动栅极一侧的衬底中。

    PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FORMING THE SAME
    24.
    发明申请
    PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FORMING THE SAME 有权
    相变记忆元件及其形成方法

    公开(公告)号：US20090250691A1

    公开(公告)日：2009-10-08

    申请号：US12203891

    申请日：2008-09-03

    申请人： Chen-Ming Huang

    发明人： Chen-Ming Huang

    IPC分类号： H01L29/18 ,  G11C11/00 ,  H01L21/06

    CPC分类号： G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1691

    摘要： A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate.

    摘要翻译： 提供了一种相变存储器及其制造方法。 相变存储元件包括：基板; 形成在基板上并且彼此平行的矩形电介质图案; 导电图案部分地覆盖电介质图案的第一侧壁和顶表面以及衬底，以暴露电介质图案的第一侧壁和第二侧壁，其中覆盖相同电介质图案的导电图案彼此分开; 形成在基板上并直接与电介质图案的暴露的第一和第二侧壁接触的相变间隔件，其中覆盖相同电介质图案的两个相邻导电图案通过相变间隔件电连接; 以及形成在基板上的电介质层。

    PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME
    25.
    发明申请
    PHASE CHANGE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME 失效
    相变存储器件及其制造方法

    公开(公告)号：US20080241741A1

    公开(公告)日：2008-10-02

    申请号：US11745980

    申请日：2007-05-08

    申请人： Chen-Ming Huang

    发明人： Chen-Ming Huang

    IPC分类号： G11B7/24

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

    摘要： Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the dielectric layer. A first conductive electrode is also embedded in the dielectric layer to penetrate the phase change material layer and extends perpendicular to a top surface of the dielectric layer.

    摘要翻译： 提供了相变存储器件及其制造方法。 相变存储器件的示例性实施例包括衬底。 介电层形成在衬底上，并且相变材料层嵌入电介质层中。 第一导电电极也嵌入电介质层中以穿透相变材料层并且垂直于电介质层的顶表面延伸。

    Split-gate memory cells and fabrication methods thereof
    26.
    发明申请
    Split-gate memory cells and fabrication methods thereof 有权
    分离栅存储单元及其制造方法

    公开(公告)号：US20080121975A1

    公开(公告)日：2008-05-29

    申请号：US11592290

    申请日：2006-11-03

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    Split-gate memory cells and fabrication methods thereof
    27.
    发明申请
    Split-gate memory cells and fabrication methods thereof 失效
    分离栅存储单元及其制造方法

    公开(公告)号：US20080105917A1

    公开(公告)日：2008-05-08

    申请号：US11785382

    申请日：2007-04-17

    申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

    IPC分类号： H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/115 ,  H01L27/11521

    摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.

    摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。 活动区域的顶层低于隔离区域的顶层。 一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。 一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

    High write and erase efficiency embedded flash cell
    29.
    发明授权
    High write and erase efficiency embedded flash cell 有权

    公开(公告)号：US07176083B2

    公开(公告)日：2007-02-13

    申请号：US10870774

    申请日：2004-06-17

    申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

    发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

    摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

    High write and erase efficiency embedded flash cell
    30.
    发明申请
    High write and erase efficiency embedded flash cell 有权
    高写入和擦除效率嵌入式闪存单元

    公开(公告)号：US20050282337A1

    公开(公告)日：2005-12-22

    申请号：US10870774

    申请日：2004-06-17

    申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

    发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

    IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

    摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

    摘要翻译： 一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间​​的结构中的源极区域，源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。