公开(公告)号：US20130107866A1

公开(公告)日：2013-05-02

申请号：US13312226

申请日：2011-12-06

Applicant: Chun-Teh Leu ,  Kun-Lin Wu ,  Wen-Hsin Wei

Inventor： Chun-Teh Leu ,  Kun-Lin Wu ,  Wen-Hsin Wei

IPC: H04B7/216 ,  H04W72/04

CPC classification number: H04W52/325 ,  H04W28/06 ,  H04W28/18 ,  H04W52/20 ,  H04W52/244 ,  H04W52/343 ,  H04W84/045

Abstract: A femtocell and a resource control method thereof are provided. The femtocell comprises a processor and a transceiver. The processor is configured to determine that a service resource of the femtocell reaches a saturation value, reduce a transmitting power of a primary common pilot channel power signal, and set a parameter of a system information block message as a barred state. The transceiver is electrically connected to the processor and configured to transmit the primary common pilot channel power signal and the system information block message.

Abstract translation: 提供了一种毫微微小区及其资源控制方法。 毫微微小区包括处理器和收发器。 处理器被配置为确定毫微微小区的服务资源达到饱和值，降低主公共导频信道功率信号的发送功率，并将系统信息块消息的参数设置为禁止状态。 收发器电连接到处理器并且被配置为发送主公共导频信道功率信号和系统信息块消息。

公开(公告)号：US20080102635A1

公开(公告)日：2008-05-01

申请号：US11965757

申请日：2007-12-28

Applicant: Kun-Lin Wu ,  Meng-Jin Tsai

Inventor： Kun-Lin Wu ,  Meng-Jin Tsai

IPC: H01L21/302

CPC classification number: H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

Abstract: A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

Abstract translation: 用于形成导电互连的化学机械抛光工艺包括以下步骤：提供其上具有第一导电线的半导体衬底，然后在衬底和第一导电线上形成至少一个电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成覆盖层。 形成盖层的方法包括使用硅烷（SiH 4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠（SiH 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，通过介电层和盖层形成通孔，以及通过通路孔与第一导电线电连接的第二导线。

公开(公告)号：US07335598B2

公开(公告)日：2008-02-26

申请号：US11109896

申请日：2005-04-19

Applicant: Kun-Lin Wu ,  Meng-Jin Tsai

Inventor： Kun-Lin Wu ,  Meng-Jin Tsai

IPC: H01L21/4763

CPC classification number: H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

Abstract translation: 用于形成金属互连的化学机械抛光工艺包括以下步骤：提供其上具有第一金属线的半导体衬底，然后在衬底和第一金属线上形成电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成薄盖层。 具有1000-3000埃厚度的薄盖层可以是例如二氧化硅层，磷硅酸盐玻璃层或富硅氧化物层。 形成覆盖层的方法包括使用硅烷（SiH 4 S 4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠（SiH 2 Cl 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，形成通过介电层和盖层的通路开口，并且形成通过通路孔与第一金属线电连接的第二金属线。

公开(公告)号：US20050186799A1

公开(公告)日：2005-08-25

申请号：US11109896

申请日：2005-04-19

Applicant: Kun-Lin Wu ,  Meng-Jin Tsai

Inventor： Kun-Lin Wu ,  Meng-Jin Tsai

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/44

CPC classification number: H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

Abstract translation: 用于形成金属互连的化学机械抛光工艺包括以下步骤：提供其上具有第一金属线的半导体衬底，然后在衬底和第一金属线上形成电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成薄盖层。 具有1000-3000埃厚度的薄盖层可以是例如二氧化硅层，磷硅酸盐玻璃层或富硅氧化物层。 形成覆盖层的方法包括使用硅烷（SiH 4 S 4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠（SiH 2 Cl 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，形成通过介电层和盖层的通路开口，并且形成通过通路孔与第一金属线电连接的第二金属线。

公开(公告)号：US06913993B2

公开(公告)日：2005-07-05

申请号：US09990948

申请日：2001-11-20

Applicant: Kun-Lin Wu ,  Meng-Jin Tsai

Inventor： Kun-Lin Wu ,  Meng-Jin Tsai

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76829 ,  H01L21/31053 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76819 ,  H01L21/7684

Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Å can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

Abstract translation: 用于形成金属互连的化学机械抛光工艺包括以下步骤：提供其上具有第一金属线的半导体衬底，然后在衬底和第一金属线上形成电介质层。 接下来，使用化学 - 机械抛光方法来抛光电介质层的表面。 此后，在抛光的介电层上形成薄盖层。 厚度在1000-3000之间的薄盖层可以是例如二氧化硅层，磷硅酸盐玻璃层或富硅氧化物层。 形成覆盖层的方法包括使用硅烷（SiH 4 S 4）或四乙基原硅酸盐（TEOS）作为主要反应剂的化学气相沉积法沉积氧化硅。 或者，可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠（SiH 2 Cl 2 Cl 2）作为主要反应剂沉积氮化硅来形成覆盖层。 最后，形成通过介电层和盖层的通路开口，并且形成通过通路孔与第一金属线电连接的第二金属线。

公开(公告)号：US06399503B1

公开(公告)日：2002-06-04

申请号：US09764329

申请日：2001-01-19

Applicant: Kun-Lin Wu ,  J. J. Huang

Inventor： Kun-Lin Wu ,  J. J. Huang

IPC: H01L21302

CPC classification number: H01L21/7684 ,  H01L21/3212

Abstract: The present invention provides a method of preventing the dishing phenomenon occurring atop a dual damascene structure on a semiconductor wafer. The semiconductor has a substrate, a first dielectric layer positioned on the substrate, a dual damascene hole positioned in the first dielectric layer through to the surface of the substrate, a barrier layer covering the surface of the first dielectric layer and both the surface of the walls and bottom of the dual damascene hole, and a copper layer positioned on the barrier layer and filling the dual damascene hole to form the dual damascene structure. The method first involves performing a first chemical mechanical polishing (CMP) process to remove portions of the copper layer down to the surface of the barrier layer. A photoresist layer is then formed atop the dual damascene structure to remove portions of the barrier layer uncovered by the photoresist layer. Finally, a second CMP process is performed to remove portions of the copper layer so as to align the top of the copper layer in the dual damascene structure with the surface of the first dielectric layer after the photoresist layer is stripped.

Abstract translation: 本发明提供一种防止半导体晶片上的双镶嵌结构顶部发生凹陷现象的方法。 半导体具有衬底，位于衬底上的第一电介质层，位于第一电介质层中的双镶嵌孔，穿过衬底的表面，覆盖第一电介质层的表面的阻挡层和 双层镶嵌孔的壁和底部，以及位于阻挡层上的铜层，并填充双镶嵌孔以形成双镶嵌结构。 该方法首先包括进行第一化学机械抛光（CMP）工艺以将铜层的部分去除到阻挡层的表面。 然后在双镶嵌结构顶部形成光致抗蚀剂层以去除未被光致抗蚀剂层覆盖的阻挡层的部分。 最后，执行第二CMP工艺以去除部分铜层，以便在剥离光致抗蚀剂层之后，将双镶嵌结构中的铜层的顶部与第一介电层的表面对准。

公开(公告)号：US06333261B1

公开(公告)日：2001-12-25

申请号：US09584697

申请日：2000-06-01

Applicant: Chi-Jung Lin ,  Jyh-J Huang ,  Horng-Bor Lu ,  Kun-Lin Wu

Inventor： Chi-Jung Lin ,  Jyh-J Huang ,  Horng-Bor Lu ,  Kun-Lin Wu

IPC: H01L2144

CPC classification number: H01L21/76843

Abstract: A semiconductor wafer includes a substrate, an aluminum layer on the substrate, an anti-reflection coating on the aluminum layer, a dielectric layer on the anti-reflection coating, and a via hole that passes through the dielectric layer and the anti-reflection coating down to a predetermined depth within the aluminum layer. A titanium layer is formed on the bottom and on the walls of the via hole. A physical vapor deposition process is then performed to form a first titanium nitride layer on the titanium layer. A chemical vapor deposition process is then performed to form a second titanium nitride layer on the first titanium nitride layer.

Abstract translation: 半导体晶片包括基板，基板上的铝层，铝层上的防反射涂层，防反射涂层上的介电层，以及穿过介电层和防反射涂层的通孔 下降到铝层内的预定深度。 在通孔的底部和壁上形成钛层。 然后进行物理气相沉积工艺以在钛层上形成第一氮化钛层。 然后进行化学气相沉积工艺以在第一氮化钛层上形成第二氮化钛层。

公开(公告)号：US06293850B1

公开(公告)日：2001-09-25

申请号：US09426937

申请日：1999-10-22

Applicant: Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Kun-Lin Wu ,  Daniel Chiu ,  Chih-Chiang Yang ,  Juan-Yuan Wu ,  Hao-Kuang Chiu

Inventor： Juen-Kuen Lin ,  Chien-Hsin Lai ,  Peng-Yih Peng ,  Kun-Lin Wu ,  Daniel Chiu ,  Chih-Chiang Yang ,  Juan-Yuan Wu ,  Hao-Kuang Chiu

IPC: B24B100

CPC classification number: B24B37/32 ,  B24B37/042 ,  B24B57/02

Abstract: A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.

公开(公告)号：US06225204B1

公开(公告)日：2001-05-01

申请号：US09168226

申请日：1998-10-07

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L2144

CPC classification number: H01L21/76825 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76831

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an implantation process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract translation: 一种用于防止在双镶嵌工艺中发生中毒的沟槽和通孔的方法，该方法包括在开口充满导电材料之前在开口周围的暴露介电层的表面上执行诸如注入工艺的致密化过程。 电介质层的致密表面能够有效地防止由脱气现象引起的中毒的沟槽和通孔的发生。

公开(公告)号：US06180467B2

公开(公告)日：2001-01-30

申请号：US09211641

申请日：1998-12-15

Applicant: Kun-Lin Wu ,  Horng-Bor Lu

Inventor： Kun-Lin Wu ,  Horng-Bor Lu

IPC: H01L21336

CPC classification number: H01L21/76224

Abstract: A method for fabricating a shallow trench isolation in a semiconductor substrate. A mask layer is formed on the substrate. The mask layer is patterned and used as a mask in order to form a trench in the substrate. A portion of the substrate is removed to form the trench in the substrate. A liner layer is formed on the substrate exposed by the trench and optionally, an additonal liner layer is formed on the liner layer. A doped isolation layer is formed to fill the trench. A densification step is performed. The mask layer is removed. The doped isolation layer has a lower glass transition temperature so that the temperature of the densification step is reduced to about 700° C. to 1000° C.

Abstract translation: 一种用于在半导体衬底中制造浅沟槽隔离的方法。 在基板上形成掩模层。 将掩模层图案化并用作掩模，以便在衬底中形成沟槽。 去除衬底的一部分以在衬底中形成沟槽。 在由沟槽暴露的衬底上形成衬里层，并且任选地，在衬垫层上形成附加衬里层。 形成掺杂隔离层以填充沟槽。 进行致密化步骤。 去除掩模层。 掺杂隔离层具有较低的玻璃化转变温度，使得致密化步骤的温度降低至约700℃至1000℃。