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    Method for forming metal wiring layer of semiconductor device
    24.
    发明授权
    Method for forming metal wiring layer of semiconductor device 有权
    用于形成半导体器件的金属布线层的方法

    公开(公告)号：US06815331B2

    公开(公告)日：2004-11-09

    申请号：US10392710

    申请日：2003-03-20

    申请人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Soo-geun Lee

    发明人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Soo-geun Lee

    IPC分类号： H01L214163

    CPC分类号： H01L21/76808 ,  H01L21/76813

    摘要： Methods for forming a metal wiring layer in a semiconductor device using a dual damascene process. In one aspect, a method for forming metal wiring in a semiconductor device comprises: forming a stopper layer on a semiconductor substrate that has a conductive layer formed thereon; forming an interlayer dielectric layer on the stopper layer; forming a hard mask layer on the interlayer dielectric layer; forming a first photoresist pattern on the hard mask layer, the first photoresist pattern having a first opening corresponding to the conductive layer; etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask to form a via hole in the interlayer dielectric layer through which a portion of the stopper layer is exposed; removing the first photoresist pattern; filling the via hole with an intermediary material layer; etching a portion of the hard mask layer to form a hard mask pattern that defines a wiring region, wherein the hard mask pattern comprises a second opening that overlaps the entire via hole or at least a portion of the via hole; removing the intermediary material layer from the via hole; forming the wiring region by etching a portion of the interlayer dielectric layer using the hard mask pattern as an etching mask; removing a portion of the stopper layer exposed by the via hole; and filling the via hole and the wiring region with a conductive material.

    摘要翻译： 使用双镶嵌工艺在半导体器件中形成金属布线层的方法。 一方面，在半导体器件中形成金属布线的方法包括：在其上形成有导电层的半导体衬底上形成阻挡层; 在所述阻挡层上形成层间绝缘层; 在所述层间介质层上形成硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂图案，所述第一光致抗蚀剂图案具有对应于所述导电层的第一开口; 使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，以在阻挡层的一部分暴露的层间绝缘层中形成通孔; 去除第一光致抗蚀剂图案; 用中间材料层填充通孔; 蚀刻硬掩模层的一部分以形成限定布线区域的硬掩模图案，其中硬掩模图案包括与整个通孔或通孔的至少一部分重叠的第二开口; 从所述通孔中去除所述中间材料层; 通过使用硬掩模图案作为蚀刻掩模蚀刻层间电介质层的一部分来形成布线区域; 去除由通孔露出的阻挡层的一部分; 以及用导电材料填充所述通孔和所述布线区域。

    Actuator for holographic information storing apparatus
    25.
    发明授权
    Actuator for holographic information storing apparatus 失效
    全息信息存储装置用致动器

    公开(公告)号：US07916371B2

    公开(公告)日：2011-03-29

    申请号：US12391569

    申请日：2009-02-24

    申请人： Young-min Cheong ,  Kyoung-woo Lee ,  Jae-hwan Kwon ,  Hyoung-jong So ,  Hong-hee Kim

    发明人： Young-min Cheong ,  Kyoung-woo Lee ,  Jae-hwan Kwon ,  Hyoung-jong So ,  Hong-hee Kim

    IPC分类号： G02B26/08

    CPC分类号： G02B26/0858

    摘要： An actuator to drive a mirror of a holographic information storing apparatus, the actuator including: piezoelectric cells; support members mounted on the piezoelectric cells; a hinge member mounted on the support member; and a post mounted on the hinge member, to support the mirror. The hinge member includes a bar disposed parallel to a rotation axis of the mirror, and a curved portion that extends from the bar.

    摘要翻译： 一种用于驱动全息信息存储装置的反射镜的致动器，所述致动器包括：压电单元; 安装在压电单元上的支撑构件; 安装在所述支撑构件上的铰链构件; 以及安装在所述铰链构件上的支撑所述反射镜的柱。 铰链构件包括平行于反射镜的旋转轴线设置的杆和从杆延伸的弯曲部分。

    Method of manufacturing semiconductor device including ultra low dielectric constant layer
    26.
    发明申请
    Method of manufacturing semiconductor device including ultra low dielectric constant layer 审中-公开
    包括超低介电常数层的半导体器件的制造方法

    公开(公告)号：US20090280637A1

    公开(公告)日：2009-11-12

    申请号：US12453326

    申请日：2009-05-07

    申请人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

    发明人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

    IPC分类号： H01L21/768

    CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31695

    摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层 半导体器件。 该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔， 形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

    Void-free metal interconnection steucture and method of forming the same
    28.
    发明申请
    Void-free metal interconnection steucture and method of forming the same 有权
    无孔金属互连结构及其形成方法

    公开(公告)号：US20050029010A1

    公开(公告)日：2005-02-10

    申请号：US10891062

    申请日：2004-07-15

    申请人： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

    发明人： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

    IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

    CPC分类号： H01L21/76877 ,  H01L21/76847

    摘要： A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

    摘要翻译： 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

    Method of manufacturing interconnection line in semiconductor device
    29.
    发明授权
    Method of manufacturing interconnection line in semiconductor device 有权
    在半导体器件中制造互连线的方法

    公开(公告)号：US06828229B2

    公开(公告)日：2004-12-07

    申请号：US10081661

    申请日：2002-02-22

    申请人： Soo-geun Lee ,  Hong-jae Shin ,  Kyoung-woo Lee ,  Jae-hak Kim

    发明人： Soo-geun Lee ,  Hong-jae Shin ,  Kyoung-woo Lee ,  Jae-hak Kim

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

    摘要： A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.

    摘要翻译： 提供了一种在半导体器件中形成互连线的方法。 在形成在半导体衬底上的下导电层上形成第一蚀刻阻挡层。 在第一蚀刻停止件上形成第一层间绝缘层。 在第一层间绝缘层上形成第二蚀刻阻挡层。 在第二蚀刻停止件上形成第二层间绝缘层。 使用第一蚀刻停止器作为蚀刻停止点，依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下导电层对准的通孔。 形成保护层以保护暴露在通孔底部的第一蚀刻终止部分。 使用第二蚀刻停止器蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点，以形成连接到通孔的沟槽。 保护层被去除。 位于通孔底部的第一蚀刻停止部分被去除。 形成填充通孔和沟槽并与下导电层电连接的上导电层。

    ACTUATOR FOR HOLOGRAPHIC INFORMATION STORING APPARATUS
    30.
    发明申请
    ACTUATOR FOR HOLOGRAPHIC INFORMATION STORING APPARATUS 失效
    用于全息信息存储设备的执行器

    公开(公告)号：US20090323150A1

    公开(公告)日：2009-12-31

    申请号：US12391569

    申请日：2009-02-24

    申请人： Young-min Cheong ,  Kyoung-woo Lee ,  Jae-hwan Kwon ,  Hyoung-jong So ,  Hong-hee Kim

    发明人： Young-min Cheong ,  Kyoung-woo Lee ,  Jae-hwan Kwon ,  Hyoung-jong So ,  Hong-hee Kim

    IPC分类号： G02B26/08

    CPC分类号： G02B26/0858

    摘要： An actuator to drive a mirror of a holographic information storing apparatus, the actuator including: piezoelectric cells; support members mounted on the piezoelectric cells; a hinge member mounted on the support member; and a post mounted on the hinge member, to support the mirror. The hinge member includes a bar disposed parallel to a rotation axis of the mirror, and a curved portion that extends from the bar.

    摘要翻译： 一种用于驱动全息信息存储装置的反射镜的致动器，所述致动器包括：压电单元; 安装在压电单元上的支撑构件; 安装在所述支撑构件上的铰链构件; 以及安装在所述铰链构件上的支柱，以支撑所述反射镜。 铰链构件包括平行于反射镜的旋转轴线设置的杆和从杆延伸的弯曲部分。