公开(公告)号：US08013367B2

公开(公告)日：2011-09-06

申请号：US11937161

申请日：2007-11-08

申请人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper

发明人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.

摘要翻译： 一种紧凑的半导体结构，其包括至少一个位于半导体衬底的表面之上和之中的FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。 在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。 在这样的实施例中，FET具有长的沟道长度。 在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。 在这样的实施例中，FET具有宽的通道宽度。 在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。 在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

公开(公告)号：US20090121261A1

公开(公告)日：2009-05-14

申请号：US11937161

申请日：2007-11-08

申请人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper

发明人： Bruce B. Doris ,  Carl J. Radens ,  Anthony K. Stamper

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.

摘要翻译： 一种紧凑的半导体结构，其包括至少一个位于半导体衬底的表面之上和之中的FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。 在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。 在这样的实施例中，FET具有长的沟道长度。 在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。 在这样的实施例中，FET具有宽的通道宽度。 在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。 在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

公开(公告)号：US20090093133A1

公开(公告)日：2009-04-09

申请号：US11869178

申请日：2007-10-09

申请人： Bruce B. Doris ,  Carl J. Radens

发明人： Bruce B. Doris ,  Carl J. Radens

IPC分类号： H01L21/47

CPC分类号： H01L29/4983 ,  B82Y30/00 ,  H01L21/28518 ,  H01L21/76831 ,  H01L23/5256 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self-assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that utilizes self-assembled block copolymer technology.

摘要翻译： 提供了一种半导体结构，其包括直接邻接至少一个图案化材料层的地形边缘的间隔件。 间隔物是自组装嵌段共聚物的不可除去的聚合物嵌段组分。 还提供了一种使用自组装嵌段共聚物技术形成包含本发明间隔物的这种半导体结构的方法。

公开(公告)号：US06806534B2

公开(公告)日：2004-10-19

申请号：US10342423

申请日：2003-01-14

申请人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L2976

CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/66553

摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.

摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。 当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。 高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。 由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

公开(公告)号：US09041116B2

公开(公告)日：2015-05-26

申请号：US13478154

申请日：2012-05-23

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

公开(公告)号：US08933515B2

公开(公告)日：2015-01-13

申请号：US13531175

申请日：2012-06-22

申请人： Stephen W. Bedell ,  Huiming Bu ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Chun-Chen Yeh

发明人： Stephen W. Bedell ,  Huiming Bu ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Chun-Chen Yeh

IPC分类号： H01L27/088 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.

摘要翻译： 一种用于制造半导体器件的半导体器件和方法包括提供具有第一应变轴的应变半导体层，在应变半导体层的表面内形成有源区，其中有源区具有沿应变轴的纵向轴线并形成栅极结构 在活跃地区。 在应变半导体层的表面上方和与栅极结构相邻的有源区上形成升高的源/漏区，以形成晶体管器件。

公开(公告)号：US08889562B2

公开(公告)日：2014-11-18

申请号：US13555306

申请日：2012-07-23

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01B13/00 ,  H01B19/04 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/32134 ,  H01L21/32137

摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

摘要翻译： 公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。 该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。 具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。 然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。 一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。 取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

公开(公告)号：US08803233B2

公开(公告)日：2014-08-12

申请号：US13242861

申请日：2011-09-23

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

IPC分类号： H01L29/778

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78654 ,  H01L29/78696

摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.

摘要翻译： 晶体管包括半导体层，并且在半导体层上形成栅极电介质。 栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。 有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。 该渐变掺杂剂区域的掺杂浓度逐渐降低。 晶体管还包括与有源区相邻的源区和漏区。 源极和漏极区域和有源区域具有相同的导电类型。

公开(公告)号：US08741701B2

公开(公告)日：2014-06-03

申请号：US13585395

申请日：2012-08-14

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Chun-Chen Yeh

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Chun-Chen Yeh

IPC分类号： H01L21/335 ,  H01L21/8232

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/66795

摘要： A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

摘要翻译： 形成半导体器件的方法包括：在基底的顶部上形成心轴; 在所述基板的顶部上形成邻近所述心轴的第一间隔件; 在第一间隔件和心轴上形成切割掩模，使得第一间隔件被切割掩模部分地暴露; 部分地去除部分暴露的第一间隔件; 并且蚀刻所述衬底以形成对应于所述衬底中部分移除的第一间隔物的翅片结构。

公开(公告)号：US08703550B2

公开(公告)日：2014-04-22

申请号：US13525642

申请日：2012-06-18

申请人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

发明人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

摘要翻译： 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。