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    Fabricating method for a metal oxide semiconductor transistor
    21.
    发明授权
    Fabricating method for a metal oxide semiconductor transistor 有权
    金属氧化物半导体晶体管的制造方法

    公开(公告)号：US07595234B2

    公开(公告)日：2009-09-29

    申请号：US11532100

    申请日：2006-09-15

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

    摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

    摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

    FABRICATING METHOD FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR
    22.
    发明申请
    FABRICATING METHOD FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
    一种金属氧化物半导体晶体管的制造方法

    公开(公告)号：US20070066041A1

    公开(公告)日：2007-03-22

    申请号：US11532100

    申请日：2006-09-15

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

    摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

    摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

    Methods of manufacturing semiconductor devices
    24.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US09349595B2

    公开(公告)日：2016-05-24

    申请号：US13546800

    申请日：2012-07-11

    申请人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsin-Chieh Yao ,  Tien-I Bao

    发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsin-Chieh Yao ,  Tien-I Bao

    IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/02

    CPC分类号： H01L21/0337 ,  H01L21/02115 ,  H01L21/31144 ,  H01L21/76816

    摘要： Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.

    摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，材料层形成在工件上。 工件包括设置在第一部分和第二部分之间的第一部分，第二部分和硬掩模。 图案化材料层，并且在图案化材料层的侧壁上形成第一间隔物。 去除图案化的材料层，并且使用第一间隔件作为蚀刻掩模来对工件的第二部分进行图案化。 去除第一间隔物，并且在工件的图案化第二部分的侧壁上形成第二间隔物。 去除工件的图案化的第二部分，并且使用第二间隔件作为蚀刻掩模来对工件的硬掩模进行图案化。 使用硬掩模作为蚀刻掩模来对工件的第一部分进行图案化。

    Self repairing process for porous dielectric materials
    25.
    发明授权
    Self repairing process for porous dielectric materials 有权
    多孔电介质材料自修复工艺

    公开(公告)号：US09029171B2

    公开(公告)日：2015-05-12

    申请号：US13531738

    申请日：2012-06-25

    申请人： Tsung-Min Huang ,  Chung-Ju Lee ,  Tien-I Bao

    发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Tien-I Bao

    IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768

    CPC分类号： H01L23/5329 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02321 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

    摘要翻译： 本公开涉及一种用于为半导体器件应用创建自修复电介质材料的结构和方法。 将多孔电介质材料沉积在基底上，并用处理剂颗粒暴露，使得处理剂颗粒扩散到电介质材料中。 在电介质材料上形成致密的无孔盖，其将电介质材料中的处理剂颗粒封装起来。 然后对电介质材料进行对电介质材料造成损伤的工艺。 在处理剂颗粒和损坏之间引发化学反应，修复损坏。 通过化学反应消耗处理剂颗粒而产生的梯度浓度促使处理剂颗粒朝向电介质材料的损坏区域的连续扩散，连续地修复损伤。

    METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
    26.
    发明申请
    METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION 有权
    半导体集成电路制造方法

    公开(公告)号：US20140065818A1

    公开(公告)日：2014-03-06

    申请号：US13599764

    申请日：2012-08-30

    申请人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76852 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature.

    摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 牺牲层（SL）在衬底上形成并图案化。 图案化SL具有多个开口。 该方法还包括在开口中形成金属层，然后移除图案化的SL以横向暴露金属层的至少一部分以形成具有与开口基本相同的轮廓的金属特征。 电介质层沉积在金属特征的侧面上。

    Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors
    27.
    发明授权
    Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors 有权
    制造应变硅晶体管和应变硅CMOS晶体管的方法

    公开(公告)号：US07491615B2

    公开(公告)日：2009-02-17

    申请号：US11162798

    申请日：2005-09-23

    申请人： Chih-Ning Wu ,  Hsin Tai ,  Chung-Ju Lee ,  Wei-Tsun Shiau

    发明人： Chih-Ning Wu ,  Hsin Tai ,  Chung-Ju Lee ,  Wei-Tsun Shiau

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

    摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.

    摘要翻译： 制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底在其上包含栅极结构; 执行蚀刻工艺以形成对应于半导体衬底内的栅极结构的两个凹部; 在半导体衬底上进行氧冲洗; 对所述半导体衬底进行清洁处理; 并且在每个用于形成源/漏区的凹槽中执行选择性外延生长（SEG）以形成外延层。

    Metal oxide semiconductor transistor
    28.
    发明授权
    Metal oxide semiconductor transistor 有权
    金属氧化物半导体晶体管

    公开(公告)号：US07214988B2

    公开(公告)日：2007-05-08

    申请号：US11162693

    申请日：2005-09-20

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： H01L29/76

    CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

    摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

    摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

    Etching process compatible with DUV lithography
    29.
    发明申请
    Etching process compatible with DUV lithography 审中-公开
    蚀刻工艺兼容DUV光刻

    公开(公告)号：US20060110688A1

    公开(公告)日：2006-05-25

    申请号：US10993593

    申请日：2004-11-19

    申请人： Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： G03F7/36

    CPC分类号： G03F7/405 ,  G03F7/40

    摘要： An etching process compatible with DUV lithography is described. A mask layer is previously formed over a material layer to be etched through a DUV lithography process of 193 nm or 157 nm. Then, plasma etching is performed to pattern the material layer using the mask layer as an etching mask, wherein the etching gas causes a protective layer to form on the surface of the mask layer. The etching gas of the plasma etching includes at least a halogen-containing gas and Xe, wherein the halogen can be F, Cl, Br or a combination thereof.

    摘要翻译： 描述了与DUV光刻相兼容的蚀刻工艺。 预先通过193nm或157nm的DUV光刻工艺在待蚀刻的材料层上形成掩模层。 然后，进行等离子体蚀刻，使用掩模层作为蚀刻掩模对材料层进行图案化，其中蚀刻气体在掩模层的表面上形成保护层。 等离子体蚀刻的蚀刻气体至少包含含卤素的气体和Xe，其中卤素可以是F，Cl，Br或其组合。