利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.023 秒)

    Methods of Manufacturing Semiconductor Devices
    1.
    发明申请
    Methods of Manufacturing Semiconductor Devices 有权
    制造半导体器件的方法

    公开(公告)号：US20140017894A1

    公开(公告)日：2014-01-16

    申请号：US13546800

    申请日：2012-07-11

    申请人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsin-Chieh Yao ,  Tien-I Bao

    发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsin-Chieh Yao ,  Tien-I Bao

    IPC分类号： H01L21/311

    CPC分类号： H01L21/0337 ,  H01L21/02115 ,  H01L21/31144 ,  H01L21/76816

    摘要： Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.

    摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，材料层形成在工件上。 工件包括设置在第一部分和第二部分之间的第一部分，第二部分和硬掩模。 图案化材料层，并且在图案化材料层的侧壁上形成第一间隔物。 去除图案化的材料层，并且使用第一间隔件作为蚀刻掩模来对工件的第二部分进行图案化。 去除第一间隔物，并且在工件的图案化第二部分的侧壁上形成第二间隔物。 去除工件的图案化的第二部分，并且使用第二间隔件作为蚀刻掩模来对工件的硬掩模进行图案化。 使用硬掩模作为蚀刻掩模来对工件的第一部分进行图案化。

    Methods of manufacturing semiconductor devices
    2.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US09349595B2

    公开(公告)日：2016-05-24

    申请号：US13546800

    申请日：2012-07-11

    申请人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsin-Chieh Yao ,  Tien-I Bao

    发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsin-Chieh Yao ,  Tien-I Bao

    IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/02

    CPC分类号： H01L21/0337 ,  H01L21/02115 ,  H01L21/31144 ,  H01L21/76816

    摘要： Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.

    摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，材料层形成在工件上。 工件包括设置在第一部分和第二部分之间的第一部分，第二部分和硬掩模。 图案化材料层，并且在图案化材料层的侧壁上形成第一间隔物。 去除图案化的材料层，并且使用第一间隔件作为蚀刻掩模来对工件的第二部分进行图案化。 去除第一间隔物，并且在工件的图案化第二部分的侧壁上形成第二间隔物。 去除工件的图案化的第二部分，并且使用第二间隔件作为蚀刻掩模来对工件的硬掩模进行图案化。 使用硬掩模作为蚀刻掩模来对工件的第一部分进行图案化。

    DIELECTRIC FORMATION
    3.
    发明申请
    DIELECTRIC FORMATION 审中-公开
    电介质形成

    公开(公告)号：US20140065816A1

    公开(公告)日：2014-03-06

    申请号：US13600504

    申请日：2012-08-31

    申请人： Tsung-Jung Tsai ,  Hsin-Chieh Yao ,  Chien-Hua Huang ,  Chung-Ju Lee

    发明人： Tsung-Jung Tsai ,  Hsin-Chieh Yao ,  Chien-Hua Huang ,  Chung-Ju Lee

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76885 ,  H01L21/76831

    摘要： Among other things, one or more techniques for forming a low k dielectric around a metal line during an integrated circuit (IC) fabrication process are provided. In an embodiment, a metal line is formed prior to forming a surrounding low k dielectric layer around the metal line. In an embodiment, the metal line is formed by filling a trench space in a skeleton layer with metal. In this embodiment, the skeleton layer is removed to form a dielectric space in a different location than the trench space. The dielectric space is then filled with a low k dielectric material to form a surrounding low k dielectric layer around the metal line. In this manner, damage to the surrounding low k dielectric layer, that would otherwise occur if the surrounding low k dielectric layer was etched, for example, is mitigated.

    摘要翻译： 其中，提供了在集成电路（IC）制造过程中用于在金属线周围形成低k电介质的一种或多种技术。 在一个实施例中，在围绕金属线形成周围的低k电介质层之前形成金属线。 在一个实施例中，通过用金属填充骨架层中的沟槽空间来形成金属线。 在该实施例中，除去骨架层以在与沟槽空间不同的位置形成电介质空间。 然后用低k电介质材料填充电介质空间，以在金属线周围形成周围的低k电介质层。 以这种方式，例如，如果周围的低k电介质层被蚀刻，则会损坏周围的低k电介质层，否则会被破坏。

    Method of semiconductor integrated circuit fabrication
    4.
    发明授权
    Method of semiconductor integrated circuit fabrication 有权
    半导体集成电路制造方法

    公开(公告)号：US08835304B2

    公开(公告)日：2014-09-16

    申请号：US13599764

    申请日：2012-08-30

    申请人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76852 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature.

    摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 牺牲层（SL）在衬底上形成并图案化。 图案化SL具有多个开口。 该方法还包括在开口中形成金属层，然后移除图案化的SL以横向暴露金属层的至少一部分以形成具有与开口基本相同的轮廓的金属特征。 电介质层沉积在金属特征的侧面上。

    METHOD OF FORMING FINE PATTERNS
    6.
    发明申请
    METHOD OF FORMING FINE PATTERNS 有权
    形成精细图案的方法

    公开(公告)号：US20140080306A1

    公开(公告)日：2014-03-20

    申请号：US13616101

    申请日：2012-09-14

    申请人： Chih Wei Lu ,  Chung-Ju Lee ,  Tien-I Bao

    发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Tien-I Bao

    IPC分类号： H01L21/311

    CPC分类号： G03F7/2022 ,  G03F7/36 ,  H01L21/31058 ,  H01L21/31144

    摘要： A method of forming a fine pattern comprises depositing a modifying layer on a substrate. A photoresist layer is deposited on the modifying layer, the photoresist layer having a first pattern. The modifying layer is etched according to the first pattern of the photoresist layer. A treatment is performed to the etched modifying layer to form a second pattern, the second pattern having a smaller line width roughness (LWR) and/or line edge roughness (LER) than the first pattern. The second pattern is then etched into the substrate.

    摘要翻译： 形成精细图案的方法包括在衬底上沉积修饰层。 光致抗蚀剂层沉积在修饰层上，光致抗蚀剂层具有第一图案。 根据光致抗蚀剂层的第一图案蚀刻修饰层。 对蚀刻的修饰层进行处理以形成第二图案，第二图案具有比第一图案更小的线宽粗糙度（LWR）和/或线边缘粗糙度（LER）。 然后将第二图案刻蚀成衬底。

    Self repairing process for porous dielectric materials
    8.
    发明授权
    Self repairing process for porous dielectric materials 有权
    多孔电介质材料自修复工艺

    公开(公告)号：US09029171B2

    公开(公告)日：2015-05-12

    申请号：US13531738

    申请日：2012-06-25

    申请人： Tsung-Min Huang ,  Chung-Ju Lee ,  Tien-I Bao

    发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Tien-I Bao

    IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768

    CPC分类号： H01L23/5329 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02321 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

    摘要翻译： 本公开涉及一种用于为半导体器件应用创建自修复电介质材料的结构和方法。 将多孔电介质材料沉积在基底上，并用处理剂颗粒暴露，使得处理剂颗粒扩散到电介质材料中。 在电介质材料上形成致密的无孔盖，其将电介质材料中的处理剂颗粒封装起来。 然后对电介质材料进行对电介质材料造成损伤的工艺。 在处理剂颗粒和损坏之间引发化学反应，修复损坏。 通过化学反应消耗处理剂颗粒而产生的梯度浓度促使处理剂颗粒朝向电介质材料的损坏区域的连续扩散，连续地修复损伤。

    METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
    9.
    发明申请
    METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION 有权
    半导体集成电路制造方法

    公开(公告)号：US20140065818A1

    公开(公告)日：2014-03-06

    申请号：US13599764

    申请日：2012-08-30

    申请人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76852 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature.

    摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 牺牲层（SL）在衬底上形成并图案化。 图案化SL具有多个开口。 该方法还包括在开口中形成金属层，然后移除图案化的SL以横向暴露金属层的至少一部分以形成具有与开口基本相同的轮廓的金属特征。 电介质层沉积在金属特征的侧面上。