公开(公告)号：US06941414B2

公开(公告)日：2005-09-06

申请号：US09855240

申请日：2001-05-15

申请人： Louis L. Hsu ,  William Wu Shen ,  Li-Kong Wang

发明人： Louis L. Hsu ,  William Wu Shen ,  Li-Kong Wang

IPC分类号： G06F12/08 ,  G06F13/42 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F12/00

CPC分类号： G11C7/106 ,  G06F12/0893 ,  G06F13/4243 ,  G06F2212/3042 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2207/2245

摘要： The invention provides a simple interface circuit between a large capacity, high speed DRAM and a single port SRAM cache to achieve fast-cycle memory performance. The interface circuit provides wider bandwidth internal communications than external data transfers. The interface circuit schedules parallel pipeline operations so that one set of data buses can be shared in cycles by several data flows to save chip area and alleviate data congestion. A flexible design is provided that can be used for a range of bandwidths of data transfer and generally any size bandwidth ranging from 32 to 4096 bits wide can use this same approach.

摘要翻译： 本发明提供了在大容量，高速DRAM和单端口SRAM缓存之间的简单接口电路，以实现快速周期的存储器性能。 接口电路提供比外部数据传输更宽的带宽内部通信。 接口电路调度并行流水线操作，使得一组数据总线可以通过几个数据流循环共享，以节省芯片面积并减轻数据拥塞。 提供了灵活的设计，可以用于数据传输的一系列带宽，一般来说，从32到4096位宽的任何大小的带宽可以使用这种相同的方法。

公开(公告)号：US06911354B2

公开(公告)日：2005-06-28

申请号：US10681464

申请日：2003-10-08

申请人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H01L21/00 ,  H01L29/786 ,  H01L51/40

CPC分类号： H01L51/057 ,  H01L51/0021

摘要： A method and structure of forming a vertical polymer transistor structure is disclosed having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconductor body layer, and an etch stop strip positioned between a portion of the first conductive layer and the semiconductor body layer.

摘要翻译： 公开了形成垂直聚合物晶体管结构的方法和结构，其具有第一导电层，与第一导电层共平面的填充结构，在第一导电层上方的半导体本体层，半导体本体层上方的第二导电层， 以及位于第一导电层的一部分和半导体本体层之间的蚀刻停止带。

公开(公告)号：US06864504B2

公开(公告)日：2005-03-08

申请号：US10453381

申请日：2003-06-03

申请人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H01L51/05 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786 ,  H01L35/24 ,  H01L51/00 ,  H01L51/40

CPC分类号： H01L51/0001 ,  H01L51/0024 ,  H01L51/0516 ,  H01L51/0541 ,  H01L51/0545

摘要： A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistor is made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.

摘要翻译： 通过使用第一平面载体来形成包括栅极，源极，漏极和主体元件的器件的第一部分来形成完全平坦化的聚合物薄膜晶体管的结构和方法。 优选地，薄膜晶体管由所有有机材料制成。 栅极电介质可以是高k聚合物，以提高器件性能。 然后，部分完成的装置结构被颠倒翻转并转移到第二平面载体。 然后施加一层蜡或光敏有机材料，并且可以用作临时胶。 然后通过蚀刻工艺限定该装置，包括其身体区域。 与器件的接触通过导电材料沉积和化学机械抛光形成。

公开(公告)号：US06825534B2

公开(公告)日：2004-11-30

申请号：US09748256

申请日：2000-12-27

申请人： Howard H. Chen ,  Louis L. Hsu ,  Li-Kong Wang

发明人： Howard H. Chen ,  Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L2701

CPC分类号： H01L21/76264 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/02689 ,  H01L21/2022 ,  H01L21/76283 ,  H01L21/84

摘要： A semiconductor device includes a combination substrate having a bulk silicon region, and a silicon-on-insulator (SOI) region. The SOI region includes a crystallized silicon layer formed by annealing amorphous silicon and having isolation trenches formed therein so as to remove defective regions, and isolation oxides formed in the isolation trenches.

摘要翻译： 半导体器件包括具有体硅区域和绝缘体上硅（SOI）区域的组合衬底。 SOI区域包括由非晶硅退火形成的结晶硅层，并且在其中形成有隔离沟槽，以去除不良区域，以及在隔离沟槽中形成隔离氧化物。

公开(公告)号：US06670234B2

公开(公告)日：2003-12-30

申请号：US09887403

申请日：2001-06-22

申请人： Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/11546

摘要： A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regions are associated with each of the gate electrodes for DRAM and flash memory cells.

摘要翻译： 在单个芯片上制造DRAM和闪存单元的方法包括提供硅衬底，为硅衬底中的每个DRAM单元形成沟槽电容器，形成硅衬底中彼此电隔离的隔离区域，形成 通过在第一预定区域中注入第一种类型的杂质，在第一种类型的阱中的第二预定区域形成用于DRAM和闪速存储单元的第二类型阱，通过植入 在第二预定区域中形成第二类型杂质，在第二类型阱上形成用于DRAM和闪存单元的氧化物层，在DRAM和闪存单元的氧化物层上形成用于DRAM的闪存存储单元的栅电极，以及形成源极和漏极 用于DRAM和闪速存储器单元的相应的第二类型阱中的用于DRAM和闪存单元的区域 e源极和漏极区域与用于DRAM和闪存单元的每个栅电极相关联。

公开(公告)号：US06664576B1

公开(公告)日：2003-12-16

申请号：US10254739

申请日：2002-09-25

申请人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

发明人： Tricia L. Breen ,  Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Kwong Hon Wong

IPC分类号： H01L27148

CPC分类号： H01L51/057 ,  H01L51/0021

摘要： A method and structure of forming a vertical polymer transistor structure is disclosed having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconductor body layer, and an etch stop strip positioned between a portion of the first conductive layer and the semiconductor body layer.

摘要翻译： 公开了形成垂直聚合物晶体管结构的方法和结构，其具有第一导电层，与第一导电层共平面的填充结构，在第一导电层上方的半导体本体层，半导体本体层上方的第二导电层， 以及位于第一导电层的一部分和半导体本体层之间的蚀刻停止带。

公开(公告)号：US06649959B2

公开(公告)日：2003-11-18

申请号：US09996731

申请日：2001-11-30

申请人： Louis L. Hsu ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L31119

CPC分类号： H01L29/66181 ,  H01L27/0805 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/945 ,  Y10S257/905 ,  Y10S438/947 ,  Y10S438/948

摘要： A method of forming a semiconductor device, includes forming at least one conductive island having a predetermined sidewall angle in a conductive substrate, forming a dielectric material over the at least one island, forming a conductive material over the dielectric material, and forming a contact to the conductive material and the at least one island.

公开(公告)号：US06621294B2

公开(公告)日：2003-09-16

申请号：US10037660

申请日：2002-01-03

申请人： Louis L. Hsu ,  Li-Kong Wang ,  Chorng-Lii Hwang

发明人： Louis L. Hsu ,  Li-Kong Wang ,  Chorng-Lii Hwang

IPC分类号： H03K1920

CPC分类号： H03K19/1737

摘要： The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at least one circuit system of the integrated circuit or device. The logic circuitry is configurable to selectively connect the at least one pad between at least two points of the at least one circuit system of the integrated circuit or device.

摘要翻译： 本发明提供了一种用于集成电路或装置的焊盘系统。 垫系统包括具有至少一个焊盘输入端子的逻辑电路，用于连接至少一个焊盘和至少两个用于连接到集成电路或设备的至少一个电路系统的输出端子。 逻辑电路可配置为在集成电路或器件的至少一个电路系统的至少两个点之间选择性地连接至少一个焊盘。

公开(公告)号：US06469949B1

公开(公告)日：2002-10-22

申请号：US09854049

申请日：2001-05-11

申请人： Louis L. Hsu ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C29/802 ,  G11C29/789

摘要： A fuse latch array system for an embedded DRAM (eDRAM) having a micro-cell architecture, a wide data bandwidth and wide internal bus width is disclosed for locatizing all the fuse information for redundancy replacement purposes. The fuse latch array system includes a fuse latch array having a plurality of memory cells where fuse information is scanned therein sequentially or parallel, or a combination thereof to be compatible with conventional fuse latch scanning protocols, during power-on. When the fuse information is stored in the fuse latch array, it is accessed as a page during a page mode operation. The accessed page contains column redundancy information corresponding to the active bank. The fuse latch array is decoded by row and column, so that the memory cell corresponding to the active bank can be easily located, even if there are thousands of banks within the eDRAM. Once the memory cell corresponding to the active bank is located, the column redundancy information is retrieved for use in identifying the defective column of the active bank using a redundant decoder. If more than one group of datalines are provided for repair, multiple parallel decoding is utilized to locate multiple defective columns simultaneously and replace them simultaneously during a redundancy operation using a conventional multiplexer circuit. The page mode operation of the fuse latch array system ensures the redundancy operation is performed within one clock cycle.

摘要翻译： 公开了一种用于具有微小区架构，宽数据带宽和宽内部总线宽度的嵌入式DRAM（eDRAM）的熔丝锁存阵列系统，用于定位所有熔丝信息用于冗余替换目的。 保险丝锁存阵列系统包括具有多个存储单元的熔丝锁存阵列，其中熔丝信息依次或并行扫描，或其组合，以在通电期间与常规熔丝锁定扫描协议兼容。 当保险丝信息存储在熔丝锁存器阵列中时，在页模式操作期间将其作为页访问。 被访问的页面包含对应于活动库的列冗余信息。 熔丝锁存器阵列由行和列进行解码，使得即使在eDRAM内有数千个存储体，也可以容易地定位对应于活动存储体的存储单元。 一旦与活动组相对应的存储单元被定位，则使用冗余解码器来检索列冗余信息以用于识别活动存储体的缺陷列。 如果提供了多组数据库进行修复，则使用多个并行解码同时定位多个有缺陷的列，并在使用常规多路复用器电路的冗余操作期间同时替换它们。 保险丝闩锁阵列系统的页面模式操作确保在一个时钟周期内执行冗余操作。

公开(公告)号：US06452110B1

公开(公告)日：2002-09-17

申请号：US09897889

申请日：2001-07-05

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Keith Kwong Hon Wong

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Keith Kwong Hon Wong

IPC分类号： H05K109

CPC分类号： H05K3/02 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/76885 ,  Y10T29/49155 ,  Y10T29/49156

摘要： A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.

摘要翻译： 一种用于生产金属聚合物导体线的方法和结构，其包括传统大马士革方法的替代方法，称为景泰蓝或逆大马士革方法。 景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。 使用标准光刻和抗蚀显影技术，将导电聚合物暴露于湿化学显影剂，除去暴露的导电聚合物区域的一部分，仅在基底顶部留下导电聚合物线。 接下来，在整个结构上沉积绝缘电介质层，并进行绝缘体的化学机械抛光平面化，产生导电聚合物线。 包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构，其包括导电聚合物，从而减少相对于现有技术的加工步骤的数量。