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公开(公告)号:US06452110B1
公开(公告)日:2002-09-17
申请号:US09897889
申请日:2001-07-05
IPC分类号: H05K109
CPC分类号: H05K3/02 , H01L21/288 , H01L21/32134 , H01L21/76885 , Y10T29/49155 , Y10T29/49156
摘要: A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.
摘要翻译: 一种用于生产金属聚合物导体线的方法和结构,其包括传统大马士革方法的替代方法,称为景泰蓝或逆大马士革方法。 景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。 使用标准光刻和抗蚀显影技术,将导电聚合物暴露于湿化学显影剂,除去暴露的导电聚合物区域的一部分,仅在基底顶部留下导电聚合物线。 接下来,在整个结构上沉积绝缘电介质层,并进行绝缘体的化学机械抛光平面化,产生导电聚合物线。 包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构,其包括导电聚合物,从而减少相对于现有技术的加工步骤的数量。
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公开(公告)号:US07041525B2
公开(公告)日:2006-05-09
申请号:US10751205
申请日:2004-01-02
CPC分类号: H01L27/14634 , H01L27/1463 , H01L27/14643
摘要: A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
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公开(公告)号:US07112502B2
公开(公告)日:2006-09-26
申请号:US10828374
申请日:2004-04-20
IPC分类号: H01L21/20
CPC分类号: H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要: A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.
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公开(公告)号:US06958522B2
公开(公告)日:2005-10-25
申请号:US09897891
申请日:2001-07-05
IPC分类号: H01L27/06 , H01L29/00 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号: H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要: A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.
摘要翻译: 集成电路芯片的方法和结构具有包括多个绝缘和导电水平的逻辑芯,外部导体水平和具有直接连接到外部导体水平的导电聚合物的无源器件。 无源器件包含还包括电阻器,电容器和/或电感器的RF器件。 电阻器可以是蛇形电阻器,电容器可以是交错电容器。
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公开(公告)号:US06720595B2
公开(公告)日:2004-04-13
申请号:US09922077
申请日:2001-08-06
IPC分类号: H01L31062
CPC分类号: H01L27/14634 , H01L27/1463 , H01L27/14643
摘要: A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
摘要翻译: 公开了一种用于光电二极管阵列的方法和结构,该阵列包括多个光电二极管芯,沿芯的外部的感光侧壁,芯之上的逻辑电路,分离芯的沟槽和沟槽中的透明材料。 利用本发明,侧壁垂直于接收入射光的光电二极管的表面。 感光侧壁包括当用光照射时引起电子转移的结区域。 侧壁包围围绕每个岛芯的四个垂直侧壁。 逻辑电路阻挡来自芯的光,因此光仅主要由侧壁感测。
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6.
公开(公告)号:US07088074B2
公开(公告)日:2006-08-08
申请号:US10039541
申请日:2002-01-02
IPC分类号: H02J7/00
CPC分类号: H01M10/425 , H01L23/58 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15153 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01M2/1066 , H01M2/204 , H01L2924/00014 , H01L2924/00
摘要: A system level device for battery and integrated circuit chip integration comprises at least one battery; at least one integrated circuit chip powered by the at least one battery; and a package connected to any of the at least one battery and the at least one integrated circuit chip, wherein the at least one battery connects to a pair of opposed upright ends of the package, wherein the at least one integrated circuit chip is disposed between the at least one battery and the package, and wherein the at least one integrated circuit chip lays on top of a portion of the package.
摘要翻译: 用于电池和集成电路芯片集成的系统级装置包括至少一个电池; 由所述至少一个电池供电的至少一个集成电路芯片; 以及连接到所述至少一个电池和所述至少一个集成电路芯片中的任一个的封装,其中所述至少一个电池连接到所述封装的一对相对的直立端,其中所述至少一个集成电路芯片设置在 所述至少一个电池和所述封装,并且其中所述至少一个集成电路芯片放置在所述封装的一部分的顶部上。
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公开(公告)号:US06768063B2
公开(公告)日:2004-07-27
申请号:US09943827
申请日:2001-08-31
IPC分类号: H05K111
CPC分类号: H05K3/24 , G01N27/226 , H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要: A method and structure for an electrode device, whereby a second electrode is deposited on a first electrode such that there is an increase in the capacitive coupling between the pair of conductive electrodes. The electrodes are self-aligning such that the patterning manufacturing process is insensitive to variations in the positional placement of the pattern on the substrate. Moreover, a single lithographic masking layer is used for forming the pair of electrodes, which are electrically isolated. Finally, the first electrode is offset from the second electrode by a chemical surface modification of the first electrode, and an anisotropic deposition of the second electrode which is shadowed by the first electrode.
摘要翻译: 一种电极装置的方法和结构,由此第二电极沉积在第一电极上,使得一对导电电极之间的电容耦合增加。 电极是自对准的,使得图案化制造工艺对图案在衬底上的位置放置的变化不敏感。 此外,单个光刻掩模层用于形成电隔离的一对电极。 最后,第一电极通过第一电极的化学表面改性和由第一电极遮蔽的第二电极的各向异性沉积而偏离第二电极。
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公开(公告)号:US07092235B2
公开(公告)日:2006-08-15
申请号:US11043760
申请日:2005-01-26
申请人: Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人: Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号: H01G4/06
摘要: A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译: 本文公开了一种用于调节形成在衬底上的片上电容器的电容的方法和装置。 多个导电层被一层电介质材料隔开。 电容器的电介质材料暴露于离子束。 离子束包括至少一种材料的离子,以改变介电材料的介电常数。
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公开(公告)号:US06869895B1
公开(公告)日:2005-03-22
申请号:US10674719
申请日:2003-09-30
申请人: Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人: Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
摘要: A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译: 用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束,以改变介电材料的介电常数。
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公开(公告)号:US07115921B2
公开(公告)日:2006-10-03
申请号:US10930989
申请日:2004-08-31
申请人: Lawrence A. Clevenger , Timothy Joseph Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人: Lawrence A. Clevenger , Timothy Joseph Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号: H01L29/80 , H01L29/76 , H01L21/337 , H01L21/336
CPC分类号: H01L21/28114 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/0629 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545
摘要: Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.
摘要翻译: 集成电路上的栅极导体形成有用于将栅极导体与其它器件电连接的较大的上部。 半导体器件包括具有扩大上部的栅极导体,该栅极导体将栅极导体电连接到局部扩散区。 另一个半导体器件包括两个栅极导体,其具有扩大的上部,其合并以产生电互连的栅极导体。 还描述和要求保护形成上述半导体器件的方法。
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