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    File system management in memory device
    23.
    发明授权
    File system management in memory device 有权

    公开(公告)号：US11500775B2

    公开(公告)日：2022-11-15

    申请号：US17184352

    申请日：2021-02-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Chun-Lien Su

    IPC: G06F12/08 ,  G06F12/084 ,  G06F12/02 ,  G06F12/0882 ,  G06F12/0871

    Abstract: A memory system stores user data including file content in clusters of memory space, folder entries, metadata, and a file allocation table FAT including FAT entries. The system comprises a cache memory, an addressable memory including memory space, and control logic coupled to the addressable memory and the cache memory. The control logic is configured to store user data in a current cluster at a current cluster offset including file content, and corresponding metadata including the current cluster offset, and a linked cluster offset of a linked cluster linking to the current cluster in the addressable memory, and to cache a FAT entry pointing to the current cluster in the cache memory.

    Memory device and read method thereof
    24.
    发明授权
    Memory device and read method thereof 有权

    公开(公告)号：US11468963B2

    公开(公告)日：2022-10-11

    申请号：US17115412

    申请日：2020-12-08

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chun-Lien Su

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/46 ,  G11C29/52

    Abstract: A memory device and a read method thereof are provided. The read method of the memory cell array includes: reading a memory cell array to obtain page data; dividing the page data into a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequence to respectively generate a plurality of first corrected chunk data; performing a second error correction operation on the page data to generate corrected page data; and outputting the corrected chunk data by referring to an indicating signal.

    FLASH MEMORY SYSTEM AND FLASH MEMORY DEVICE THEREOF
    26.
    发明申请
    FLASH MEMORY SYSTEM AND FLASH MEMORY DEVICE THEREOF 有权

    公开(公告)号：US20220188238A1

    公开(公告)日：2022-06-16

    申请号：US17118239

    申请日：2020-12-10

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chun-Lien Su ,  Chun-Hsiung Hung ,  Shuo-Nan Hung

    IPC: G06F12/0882 ,  G06F12/0862 ,  G06F12/02 ,  G06F11/10

    Abstract: A flash memory system and a flash memory thereof are provided. The flash memory device includes a NAND flash memory and a control circuit. The NAND flash memory chip includes a cache memory, a page buffer; and an NAND flash memory array. The NAND flash memory array includes a plurality of pages, wherein each page includes a plurality of sub-pages, each sub-page has a sub-page length. The cache memory is composed of a plurality of sub cache and each sub cache corresponds to different pages of the NAND flash memory array. The page buffer is composed of a plurality of sub-page buffers and each sub-page buffer corresponds to different pages of the NAND flash memory array. The control circuit is coupled to the host and the NAND flash memory, and performs an access operation in units of one sub-page.

    Non-volatile register and implementation of non-volatile register
    27.
    发明授权
    Non-volatile register and implementation of non-volatile register 有权

    公开(公告)号：US11074975B1

    公开(公告)日：2021-07-27

    申请号：US16841711

    申请日：2020-04-07

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chun-Lien Su ,  Ming-Shang Chen

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  H01L27/1157 ,  H01L27/11524

    Abstract: A non-volatile register is provided. The non-volatile register includes a plurality of cell strings with respect to a plurality of bit lines, wherein each cell string includes a plurality of cells. Each word line is respectively connecting to a gate of one cell for each cell string to correspondingly form a page. The pages are configured into: a central page used as a register to store registered data; and a plurality of dummy pages at both sides of the central page. The dummy pages are controlled to provide a boosted channel voltage to a portion of memory cells of the central page, not being programmed. A source selection transistor is connected to a first side for each cell string. A drain selection transistor is connected to a second side for each cell string.

    Data transfer between memory devices on shared bus
    28.
    发明授权
    Data transfer between memory devices on shared bus 有权

    公开(公告)号：US10936234B2

    公开(公告)日：2021-03-02

    申请号：US16419298

    申请日：2019-05-22

    Applicant: Macronix International Co., Ltd.

    Inventor： Chun-Lien Su

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Systems, devices, and methods for data transfer between memory devices on a shared bus are provided. In one aspect, a system includes first and second memory devices and a shared bus. A host device is configured to send at least one control signal through the shared bus to the first and second memory devices, and the control signal specifies data to be transferred from the first memory device to the second memory device. In response to receiving the control signal, the first memory device is configured to read and transmit the data to the shared bus, and the second memory device is configured to receive the data from the shared bus and write the data in the second memory device. The data is transferred directly from the first memory device to the second memory device through the shared bus without passing through the host device.

    Manufacturing method of non-volatile memory
    29.
    发明授权
    Manufacturing method of non-volatile memory 有权
    非易失性存储器的制造方法

    公开(公告)号：US08859364B2

    公开(公告)日：2014-10-14

    申请号：US14153897

    申请日：2014-01-13

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Shaw-Hung Ku ,  Chi-Pei Lu ,  Chun-Lien Su

    IPC: H01L21/336 ,  H01L29/788 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

    CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7881

    Abstract: The present invention provides a manufacturing method of a non-volatile memory including forming a gate dielectric layer on a substrate; forming a floating gate on the gate dielectric layer; forming a first charge blocking layer on the floating gate; forming a nitride layer on the first charge blocking layer; forming a second charge blocking layer on the nitride layer; forming a control gate on the second charge blocking layer; and performing a treatment to the nitride layer to get a higher dielectric constant.

    Abstract translation: 本发明提供了一种非易失性存储器的制造方法，包括在衬底上形成栅介质层; 在栅介质层上形成浮栅; 在浮栅上形成第一电荷阻挡层; 在所述第一电荷阻挡层上形成氮化物层; 在所述氮化物层上形成第二电荷阻挡层; 在所述第二电荷阻挡层上形成控制栅极; 并对氮化物层进行处理以获得更高的介电常数。

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