公开(公告)号：US09070753B1

公开(公告)日：2015-06-30

申请号：US14327255

申请日：2014-07-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Hsiung Lee ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/7688 ,  H01L27/11573 ,  H01L29/66833

Abstract: Provided is a method for fabricating a memory device. A stack layer, including a storage layer, a first conductive layer and a first mask layer, is formed on the substrate in a first region and a second region. The stack layer is patterned to form a plurality of first patterned stack layers extending along a first direction and from the first region to the second region. Two sides of each first patterned stack layers have openings respectively. A filling layer is formed on the substrate, and filled in the openings. A second mask layer is formed on the second region, and does not cover the filling layer in the second region. Then, using the second mask layer and the filling layer as mask, the first patterned stack layers and part of the substrate are removed, and a plurality of trenches are formed in the substrate in the second region.

Abstract translation: 提供一种用于制造存储器件的方法。 在第一区域和第二区域中的衬底上形成包括存储层，第一导电层和第一掩模层的堆叠层。 图案化堆叠层以形成沿着第一方向从第一区域延伸到第二区域的多个第一图案化堆叠层。 每个第一图案化叠层的两侧分别具有开口。 填充层形成在基板上并填充在开口中。 第二掩模层形成在第二区域上，并且不覆盖第二区域中的填充层。 然后，使用第二掩模层和填充层作为掩模，去除第一图案化堆叠层和衬底的一部分，并且在第二区域中的衬底中形成多个沟槽。

公开(公告)号：US09036393B2

公开(公告)日：2015-05-19

申请号：US14063284

申请日：2013-10-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming-Shang Chen

IPC: G11C17/06 ,  G11C17/16 ,  H01L21/822 ,  H01L27/10 ,  H01L27/06

CPC classification number: G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

公开(公告)号：US20240355732A1

公开(公告)日：2024-10-24

申请号：US18302804

申请日：2023-04-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Chih-Kai Yang ,  Tzung-Ting Han

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.

公开(公告)号：US12048154B2

公开(公告)日：2024-07-23

申请号：US17344661

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Tzung-Ting Han ,  Lo Yueh Lin ,  Chih-Chin Chang ,  Yu-Fong Huang ,  Yu-Hsiang Yeh

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

公开(公告)号：US11727971B2

公开(公告)日：2023-08-15

申请号：US17131437

申请日：2020-12-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L27/11582 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes a substrate, a stack structure, a first staircase structure, and a first part of a second staircase structure. The substrate includes a plurality of blocks each having a staircase region, a memory array region, and a word line cutting region. The stack structure is located on the substrate in the memory array region, and includes first insulating layers and conductive layers alternately stacked on each other. The first staircase structure is located on the substrate in the staircase region, and includes first insulating layers and conductive layers alternately stacked on each other. The first part of the second staircase structure is located on the substrate in the word line cutting region, and includes first insulating layers and conductive layers alternately stacked on each other, and two first parts of two second staircase structures in two adjacent blocks are separated from each other.

公开(公告)号：US11610842B2

公开(公告)日：2023-03-21

申请号：US17109960

申请日：2020-12-02

Applicant: MACRONIX International Co., Ltd.

Inventor： Ching Hung Wang ,  Shih Chin Lee ,  Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529

Abstract: Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

公开(公告)号：US20220302168A1

公开(公告)日：2022-09-22

申请号：US17836799

申请日：2022-06-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Kai Yang ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/768 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/00 ,  H01L27/1157

Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.

公开(公告)号：US20220123009A1

公开(公告)日：2022-04-21

申请号：US17075480

申请日：2020-10-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Chien-Ying Lee ,  Chih-Hsiung Lee ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Provided is a memory device including a substrate, a stack structure on the substrate, a contact, and a supporting pillar. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The contact is connected to one of the plurality of conductive layers of the stack structure. The supporting pillar penetrates the stack structure and is disposed around the contact. The supporting pillar includes a body portion and a plurality of extension portions. The body portion is arranged around a first side of the contact. The plurality of extension portions are located on two sides of the body portion. A length of each of the extension portions is greater than a width of the contact, and one of the extension portions is disposed around a second side of the contact.

公开(公告)号：USRE46970E1

公开(公告)日：2018-07-24

申请号：US15207201

申请日：2016-07-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming-Shang Chen

IPC: G11C17/06 ,  G11C17/16 ,  H01L21/822 ,  H01L27/10 ,  H01L27/06

CPC classification number: G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

公开(公告)号：US09847339B2

公开(公告)日：2017-12-19

申请号：US15096560

申请日：2016-04-12

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Min Hung ,  Chien-Ying Lee ,  Tzung-Ting Han

IPC: H01L21/768 ,  H01L27/11521 ,  H01L23/528 ,  H01L29/788 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L27/11521 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L28/00 ,  H01L29/7883

Abstract: Various embodiments provide a self-merged profile (SMP) method for fabricating a semiconductor device and a device fabricated using an SMP method. In an example embodiment, a semiconductor device is provided. The example semiconductor device comprises (a) a plurality of conductive lines; (b) a plurality of conductive pads; (c) a plurality of dummy tails; and (d) a plurality of closed loops. Each of the plurality of conductive pads is associated with one of the plurality of conductive lines, one of the plurality of dummy tails, and one of the plurality of closed loops. In example embodiments, the plurality of dummy tails and the plurality of closed loops are formed as residuals of the process used to create the plurality of conductive lines and the plurality of conductive pads.