公开(公告)号：US20190179698A1

公开(公告)日：2019-06-13

申请号：US15835859

申请日：2017-12-08

Applicant: Macronix International Co., Ltd.

Inventor： Ting-Yu Liu ,  Yi-Chun Liu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F11/1048 ,  G06F3/064 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7208

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing data arrangement in a super block in a memory such as NAND flash memory are provided. In one aspect, a memory controller includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to determine one or more characteristics of data to be written, allocate a super page of a super block based on the determined characteristics of the data and block information of the physical blocks of the planes, the super block combining one or more physical blocks from the planes, the super page combining one or more single pages from the corresponding one or more physical blocks in the super block, arrange the data to the one or more single pages in the super page, and program the super page to write the data in the one or more single pages.

公开(公告)号：US11798640B2

公开(公告)日：2023-10-24

申请号：US17566080

申请日：2021-12-30

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu

IPC: G06F3/06 ,  G11C16/34 ,  G06F11/10 ,  G11C29/00 ,  G11C11/56 ,  G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C29/42

CPC classification number: G11C16/3431 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/1004 ,  G06F11/1072 ,  G11C11/5635 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/349 ,  G11C16/3459 ,  G11C29/42 ,  G11C29/789

Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

公开(公告)号：US20220253352A1

公开(公告)日：2022-08-11

申请号：US17730548

申请日：2022-04-27

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu ,  Wei Jie Chen ,  Ching Ting Lu ,  Zheng Wu

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G11C16/08 ,  G06F12/0882 ,  G11C16/34 ,  G11C16/14 ,  G06F12/02

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: evaluating a read disturbance level of an open block in a memory, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, managing each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.

公开(公告)号：US10719390B2

公开(公告)日：2020-07-21

申请号：US16208601

申请日：2018-12-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Chun Liu

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52

Abstract: A memory system, a controller, a memory and a reading method thereof are provided. The reading method includes the following steps. A plurality of duplicated contents which are formed by duplicating one data content several times are received by a voting circuit. A voting procedure is performed by the voting circuit to obtain a voted content which is a majority of the duplicated contents.

公开(公告)号：US20190095364A1

公开(公告)日：2019-03-28

申请号：US15712456

申请日：2017-09-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tzu-Yi Yang ,  Yi-Chun Liu

IPC: G06F13/16 ,  G06F3/06 ,  G11C16/14

Abstract: A controlling method, a channel operating circuit and a memory system for executing a plurality of memory dies with single channel are provided. The plurality of memory dies correspond to a plurality of queue sections of a command queue. The controlling method comprises the following steps: A selecting unit selects one of the plurality of queue sections corresponding one of the plurality of memory dies which is riot at a busy state. An executing unit executes a command stored in one of the plurality of queue sections which is selected.

公开(公告)号：US10210097B2

公开(公告)日：2019-02-19

申请号：US15375545

申请日：2016-12-12

Applicant: Macronix International Co., Ltd.

Inventor： Tzu-Yi Yang ,  Ting-Yu Liu ,  Yi-Chun Liu

IPC: G06F12/121 ,  G06F3/06

Abstract: A request is received to load a particular overlay segment from a secondary storage memory to a main memory for execution by a processor, wherein the particular overlay segment is absent from the main memory. A determination is made whether the main memory can receive the particular overlay segment. In response to determining that the main memory cannot receive the particular overlay segment, eviction strategy information about one or more existing overlay segments that are present in the main memory is obtained. Based on the eviction strategy information, at least one of the one or more existing overlay segments is selected for eviction from the main memory. The particular overlay segment is retrieved from the secondary storage memory. The at least one of the one or more existing overlay segments in the main memory that is selected for eviction is replaced with the particular overlay segment.

公开(公告)号：US09984759B1

公开(公告)日：2018-05-29

申请号：US15471262

申请日：2017-03-28

Applicant: Macronix International Co., Ltd.

Inventor： Yuchih Yeh ,  Yi-Chun Liu ,  Naiping Kuo

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C29/50 ,  H03M13/05

CPC classification number: G11C16/3427 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/50004 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/5004 ,  H03M13/05

Abstract: Systems, methods, and apparatus including computer-readable mediums for detecting data integrity, e.g., read disturbance and/or data retention, of memory systems such as NAND flash memory devices are provided. For detection of read disturbance, an indicator string in a block of a memory can be filled with a predetermined state and read with a special read condition to check read disturbance of the block in one read operation. For detection of data retention, a page of a dedicated block in a memory can be chosen as an indicator page. The indicator page can be filled with a predetermined pattern and read with a proper voltage to quantify a retention shift and further to evaluate other data blocks in the memory with the qualified retention shift. The techniques enable a quick method to examine memory and help to refresh memory before data corruption.

公开(公告)号：US09959044B2

公开(公告)日：2018-05-01

申请号：US15145504

申请日：2016-05-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ting-Yu Liu ,  Nai-Ping Kuo ,  Yi-Chun Liu ,  Jian-Shing Liu

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/0605 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/068 ,  G06F12/0246 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/657

Abstract: A memory device includes a first storage unit storing an address mapping table, and a control unit coupled to the first storage unit and including a second storage unit storing a risky mapping table and a cached mapping table. The control unit is configured to: write data into the first storage unit; update mapping information associated with the data in the risky mapping table; and store mapping information in the cached mapping table into the address mapping table.