公开(公告)号：US11942439B2

公开(公告)日：2024-03-26

申请号：US17744297

申请日：2022-05-13

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Yung-Chang Lien

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3185 ,  H01L23/3675 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate has a wiring structure and is surrounded by a molding material. The frame is disposed in the molding material and surrounds the substrate. The redistribution layer is disposed over the substrate and electrically coupled to the wiring structure. The first semiconductor die is disposed over the redistribution layer.

公开(公告)号：US11791266B2

公开(公告)日：2023-10-17

申请号：US17886704

申请日：2022-08-12

Applicant: MediaTek Inc.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3171 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.

公开(公告)号：US20230187377A1

公开(公告)日：2023-06-15

申请号：US17987873

申请日：2022-11-16

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Chih-Ming Hung ,  Shih-Chia Chiu

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/66 ,  H01Q1/38

CPC classification number: H01L23/552 ,  H01L25/0655 ,  H01L24/16 ,  H01L25/105 ,  H01L23/49833 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49816 ,  H01L23/66 ,  H01Q1/38 ,  H01L2924/1431 ,  H01L2924/1421 ,  H01L2924/2027 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2224/1601 ,  H01L2225/1023 ,  H01L23/145

Abstract: A semiconductor package includes a base film, a semiconductor die on the base film, metal studs on the semiconductor die, shielding pillars on the base film and around the semiconductor die, a first molding compound encapsulating the semiconductor die, the metal studs, and the shielding pillars, a first re-distribution structure on the first molding compound, a second molding compound on the first re-distribution structure, through-mold-vias in the second molding compound, and a second re-distribution structure on the second molding compound and electrically connected to the through-mold-vias. The second re-distribution structure comprises an antenna.

公开(公告)号：US20230073399A1

公开(公告)日：2023-03-09

申请号：US17989498

申请日：2022-11-17

Applicant: MediaTek Inc.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

公开(公告)号：US11508678B2

公开(公告)日：2022-11-22

申请号：US16910354

申请日：2020-06-24

Applicant: MEDIATEK INC.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Tzu-Hung Lin

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01Q1/22 ,  H01Q1/38

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes an antenna device and semiconductor package. The antenna device includes a conductive pattern layer including a first antenna element, formed in an insulating substrate and adjacent to a first surface of the insulating substrate. The antenna device also includes a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The semiconductor package includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer. The semiconductor package also includes a first semiconductor die electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first semiconductor die.

公开(公告)号：US10431564B2

公开(公告)日：2019-10-01

申请号：US14539180

申请日：2014-11-12

Applicant: MediaTek inc.

Inventor： Tzu-Hung Lin

IPC: H01L23/36 ,  H01L25/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/498 ,  H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a chip package over a printed circuit board and multiple conductive bumps between the chip package and the printed circuit board. The chip package structure also includes one or more thermal conductive elements between the chip package and the printed circuit board. The thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps.

公开(公告)号：US20190295980A1

公开(公告)日：2019-09-26

申请号：US16439707

申请日：2019-06-13

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Thomas Matthew Gregorich

IPC: H01L23/00 ,  H01L23/498

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

公开(公告)号：US10410969B2

公开(公告)日：2019-09-10

申请号：US15891481

申请日：2018-02-08

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Chia-Cheng Chang ,  I-Hsuan Peng

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/367 ,  H01L25/10

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package overlying a portion of the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure, a first semiconductor die and a molding compound. The first semiconductor die is disposed on a first surface of the first RDL structure and electrically coupled to the first RDL structure. The molding compound is positioned overlying the first semiconductor die and the first surface of the first RDL structure. The second semiconductor package includes a first memory die and a second memory die vertically stacked on the first memory die. The second memory die is electrically coupled to first memory die by through silicon via (TSV) interconnects formed passing through the second memory die.

公开(公告)号：US10217723B2

公开(公告)日：2019-02-26

申请号：US15644849

申请日：2017-07-10

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu ,  Wei-Che Huang

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538 ,  H01L29/06

Abstract: A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.

公开(公告)号：US09978729B2

公开(公告)日：2018-05-22

申请号：US14986207

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  I-Hsuan Peng

IPC: H01L23/02 ,  H01L25/10 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on a bottom surface of the first molding compound. The first semiconductor die is coupled to the first RDL structure. A second redistribution layer (RDL) structure is disposed on a top surface of the first molding compound. A passive device is coupled to the second RDL structure.