公开(公告)号：US12119958B2

公开(公告)日：2024-10-15

申请号：US18349148

申请日：2023-07-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: H04L12/4625 ,  G06F13/4027 ,  G06F13/4208 ,  G06F15/17331 ,  H04L12/4633 ,  G06F2213/0026

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US20240143528A1

公开(公告)日：2024-05-02

申请号：US17979013

申请日：2022-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Eliav Bar-Ilan ,  Ran Avraham Koren ,  Liran Liss ,  Oren Duer ,  Shahaf Shuler

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0024

Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.

公开(公告)号：US20240095205A1

公开(公告)日：2024-03-21

申请号：US17987904

申请日：2022-11-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Liran Liss ,  Aviad Shaul Yehezkel ,  Rabia Loulou ,  Oren Duer ,  Shahaf Shuler ,  Chenghuan Jia ,  Philip Browning Johnson ,  Gal Shalom ,  Omri Kahalon ,  Adi Merav Horowitz ,  Arpit Jain ,  Eliav Bar-Ilan ,  Prateek Srivastava

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4022 ,  G06F13/404

Abstract: A system includes a bus interface and circuitry. The bus interface is configured to communicate with an external device over a peripheral bus. The circuitry is configured to support a plurality of widgets that perform primitive operations used in implementing peripheral-bus devices, to receive a user-defined configuration, which specifies a user-defined peripheral-bus device as a configuration of one or more of the widgets, and to implement the user-defined peripheral-bus device toward the external device over the peripheral bus, in accordance with the user-defined configuration.

公开(公告)号：US11909660B2

公开(公告)日：2024-02-20

申请号：US17987911

申请日：2022-11-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Yamin Friedman ,  Daniel Marcovitch ,  Gil Levy

IPC: H04L47/34 ,  H04L1/18

CPC classification number: H04L47/34 ,  H04L1/18

Abstract: In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the tinier is activated responsively to a quantity of the multiple missing data packets.

公开(公告)号：US11880711B2

公开(公告)日：2024-01-23

申请号：US18071692

申请日：2022-11-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Roman Nudelman ,  Gil Bloch ,  Daniel Marcovitch

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/30065 ,  G06F9/485 ,  G06F9/542

Abstract: A processing device includes an interface and one or more processing circuits. The interface is to connect to a host processor. The one or more processing circuits are to receive from the host processor, via the interface, a notification specifying an operation for execution by the processing device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks, in response to the notification, to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation in accordance with the schedule.

公开(公告)号：US20240012753A1

公开(公告)日：2024-01-11

申请号：US17858104

申请日：2022-07-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Yossef Itigin ,  Ortal Ben Moshe ,  Roman Nudelman

IPC: G06F12/06 ,  G06F12/0831 ,  G06F15/173 ,  G06F13/40

CPC classification number: G06F12/0653 ,  G06F12/0835 ,  G06F15/17331 ,  G06F13/4027

Abstract: A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.

公开(公告)号：US11556378B2

公开(公告)日：2023-01-17

申请号：US17120321

申请日：2020-12-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Roman Nudelman ,  Gil Bloch ,  Daniel Marcovitch

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/54

Abstract: A network device includes a network interface, a host interface and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host including a processor. The processing circuitry is configured to receive from the processor, via the host interface, a notification specifying an operation for execution by the network device, the operation including (i) multiple tasks that are executable by the network device, and (ii) execution dependencies among the tasks in response to the notification, the processing circuitry is configured to determine a schedule for executing the tasks, the schedule complying with the execution dependencies, and to execute the operation by executing the tasks of the operation is accordance with the schedule.

公开(公告)号：US20220217101A1

公开(公告)日：2022-07-07

申请号：US17142366

申请日：2021-01-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Ariel Shahar ,  Gil Bloch ,  Lior Narkis

IPC: H04L12/879 ,  H04L12/861 ,  H04L12/937 ,  H04L12/24

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.

公开(公告)号：US12265497B2

公开(公告)日：2025-04-01

申请号：US17977894

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Richard Graham

IPC: G06F15/173 ,  G06F13/32

Abstract: Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of remote direct memory access (RDMA) operations. The techniques include but are not limited to unified RDMA operations that are recognizable by various communicating devices, such as network controllers and target memory devices, as requests to establish, set, and/or update arrival indicators in the target memory devices responsive to arrival of one or more portions of the data being communicated.

公开(公告)号：US12248416B2

公开(公告)日：2025-03-11

申请号：US18655386

申请日：2024-05-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Eliav Bar-Ilan ,  Ran Avraham Koren ,  Liran Liss ,  Oren Duer ,  Shahaf Shuler

IPC: G06F13/28 ,  G06F13/42

Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.