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    Reducing size of completion notifications
    21.
    发明申请
    Reducing size of completion notifications 有权
    减少完成通知的大小

    公开(公告)号：US20140143454A1

    公开(公告)日：2014-05-22

    申请号：US13682772

    申请日：2012-11-21

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Ofer Hayut ,  Noam Bloch ,  Michael Kagan ,  Ariel Shachar

    IPC: G06F3/01

    CPC classification number: G06F3/016 ,  G06F13/128 ,  G06F13/14

    Abstract: A computer peripheral device includes a host interface, which is configured to communicate over a bus with a host processor and with a system memory of the host processor. Processing circuitry in the peripheral device is configured to receive and execute work items submitted to the peripheral device by client processes running on the host processor, and responsively to completing execution of the work items, to write completion reports to the system memory, including first completion reports of a first data size and second completion reports of a second data size, which is smaller than the first data size.

    Abstract translation: 计算机外围设备包括主机接口，其被配置为通过总线与主处理器和主机处理器的系统存储器进行通信。 外围设备中的处理电路被配置为通过在主处理器上运行的客户端进程来接收和执行提交给外围设备的工作项目，并响应于完成工作项目的执行，将完成报告写入系统存储器，包括首次完成 报告第一数据大小和第二数据大小的第二完成报告，其小于第一数据大小。

    Regrouping of video data in host memory
    24.
    发明授权
    Regrouping of video data in host memory 有权

    公开(公告)号：US11700414B2

    公开(公告)日：2023-07-11

    申请号：US17542426

    申请日：2021-12-05

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan David Levi ,  Michael Kagan

    IPC: H04N21/00 ,  H04N21/426 ,  G06T1/60

    CPC classification number: H04N21/42607 ,  G06T1/60 ,  H04N21/42653

    Abstract: Apparatus for data communications includes a host interface, which is configured to be connected to a bus of a host computer having a processor and a memory. Processing circuitry, which is coupled to the host interface, is configured to receive video data with respect to a sequence of pixels, the video data including data words of more than eight bits per pixel for at least one pixel component of the pixels, and to write the video data, via the host interface, to at least one buffer in the memory while justifying the video data in the memory so that the successive pixels in the sequence are byte-aligned in the at least one buffer.

    NIC with switching functionality between network ports
    25.
    发明授权
    NIC with switching functionality between network ports 有权

    公开(公告)号：US10454991B2

    公开(公告)日：2019-10-22

    申请号：US14658260

    申请日：2015-03-16

    Applicant: Mellanox Technologies Ltd.

    Inventor： Noam Bloch ,  Ariel Shachar ,  Michael Kagan ,  Lior Narkis ,  Shlomo Raikin

    IPC: H04L29/08 ,  G06F9/455

    Abstract: A network interface device includes a host interface for connection to a host processor and a network interface, which is configured to transmit and receive data packets over a network, and which comprises multiple distinct physical ports configured for connection to the network. Processing circuitry is configured to receive, via one of the physical ports, a data packet from the network and to decide, responsively to a destination identifier in the packet, whether to deliver a payload of the data packet to the host processor via the host interface or to forward the data packet to the network via another one of the physical ports.

    Handling transport layer operations received out of order
    26.
    发明授权
    Handling transport layer operations received out of order 有权

    公开(公告)号：US10110518B2

    公开(公告)日：2018-10-23

    申请号：US14132014

    申请日：2013-12-18

    Applicant: Mellanox Technologies Ltd.

    Inventor： Idan Burstein ,  Michael Kagan ,  Noam Bloch ,  Ariel Shachar ,  Hillel Chapman ,  Dror Bohrer ,  Diego Crupnicoff

    IPC: H04L12/861 ,  H04L12/879 ,  H04L29/08 ,  G06F15/173

    Abstract: A method for communication includes receiving at a receiving node over a network from a sending node a succession of data packets belonging to a sequence of transactions, including at least one or more first packets belonging to a first transaction and one or more second packets belonging to a second transaction executed by the sending node after the first transaction, wherein at least one of the second packets is received at the receiving node before at least one of the first packets. At the receiving node, upon receipt of the data packets, data are written from the data packets in the succession to respective locations in a buffer. Execution of the second transaction at the receiving node is delayed until all of the first packets have been received and the first transaction has been executed at the receiving node.

    ADDRESS TRANSLATION SERVICES FOR DIRECT ACCESSING OF LOCAL MEMORY OVER A NETWORK FABRIC
    29.
    发明申请
    ADDRESS TRANSLATION SERVICES FOR DIRECT ACCESSING OF LOCAL MEMORY OVER A NETWORK FABRIC 有权
    地址翻译服务，用于直接访问网络织物上的本地记忆

    公开(公告)号：US20160077976A1

    公开(公告)日：2016-03-17

    申请号：US14953462

    申请日：2015-11-30

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Shlomo Raikin ,  Idan Burstein ,  Adi Menachem ,  Michael Kagan

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/385 ,  G06F2212/657

    Abstract: A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address.

    Abstract translation: 一种系统中的方法，包括通过结构上的彼此通信的第一和第二设备，所述结构根据结构地址空间操作，并且其中所述第二设备经由本地连接而不是所述结构访问本地存储器，包括 从第一设备向翻译代理（TA）发送指定第一设备所运行的地址空间中的非翻译地址的翻译请求，用于直接访问第二设备的本地存储器。 指定第一设备将使用而不是非翻译地址的结构地址空间中的相应翻译地址的翻译响应由第一设备接收。 第二设备的本地存储器通过将非翻译地址转换为转换的地址，由第一设备直接通过结构访问。

    System and method for accelerating input/output access operation on a virtual machine
    30.
    发明授权
    System and method for accelerating input/output access operation on a virtual machine 有权
    用于加速虚拟机上输入/输出访问操作的系统和方法

    公开(公告)号：US09003418B2

    公开(公告)日：2015-04-07

    申请号：US14011767

    申请日：2013-08-28

    Applicant: Mellanox Technologies Ltd.

    Inventor： Michael Kagan ,  Dror Goldenberg ,  Benny Koren ,  Michael Tsirkin

    IPC: G06F9/46 ,  G06F9/455 ,  G06F13/12

    CPC classification number: G06F9/45558 ,  G06F13/12

    Abstract: A system and method for accelerating input/output (IO) access operation on a virtual machine, The method comprises providing a smart IO device that includes an unrestricted command queue (CQ) and a plurality of restricted CQs and allowing a guest domain to directly configure and control IO resources through a respective restricted CQ, the IO resources allocated to the guest domain. In preferred embodiments, the allocation of IO resources to each guest domain is performed by a privileged virtual switching element. In some embodiments, the smart IO device is a HCA and the privileged virtual switching element is a Hypervisor.

    Abstract translation: 一种用于加速虚拟机上的输入/输出（IO）访问操作的系统和方法，该方法包括提供包括不受限制的命令队列（CQ）和多个受限CQ的智能IO设备，并允许来宾域直接配置 并通过相应的限制CQ来控制IO资源，分配给访客域的IO资源。 在优选实施例中，IO资源到每个访客域的分配由特权虚拟交换元件执行。 在一些实施例中，智能IO设备是HCA，并且特权虚拟交换元件是管理程序。

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