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    Memory read operation using a voltage pattern based on a read command type
    21.
    发明授权
    Memory read operation using a voltage pattern based on a read command type 有权

    公开(公告)号：US11972122B2

    公开(公告)日：2024-04-30

    申请号：US17817465

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

    Enhanced gradient seeding scheme during a program operation in a memory sub-system
    24.
    发明授权
    Enhanced gradient seeding scheme during a program operation in a memory sub-system 有权

    公开(公告)号：US11901010B2

    公开(公告)日：2024-02-13

    申请号：US17247576

    申请日：2020-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/30 ,  G11C16/08

    CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

    Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

    3D NAND MEMORY WITH BUILT-IN CAPACITOR
    25.
    发明公开
    3D NAND MEMORY WITH BUILT-IN CAPACITOR 审中-公开

    公开(公告)号：US20240046998A1

    公开(公告)日：2024-02-08

    申请号：US17879356

    申请日：2022-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

    IPC: G11C16/30

    CPC classification number: G11C16/30

    Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.

    MEMORY OPERATION BASED ON BLOCK-ASSOCIATED TEMPERATURE
    26.
    发明公开
    MEMORY OPERATION BASED ON BLOCK-ASSOCIATED TEMPERATURE 审中-公开

    公开(公告)号：US20230418475A1

    公开(公告)日：2023-12-28

    申请号：US17848061

    申请日：2022-06-23

    Applicant: Micron Technology, Inc.

    Inventor： Pitamber Shukla ,  Ching-Huang Lu ,  Devin Batutis

    IPC: G06F3/06 ,  G06F11/07 ,  G06F11/00

    CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/002

    Abstract: Various embodiments provide for performing a memory operation, such as a memory block compaction operation or block folding or refresh operation, based on a temperature associated with a memory block of a memory device. For instance, some embodiments provide for techniques that can cause performance of a block compaction operation on a memory block at a temperature that is at least at or higher than a predetermined temperature value. Additionally, some embodiments provide for techniques that can cause performance of a block folding/refresh operation, at a temperature that is at or higher than the predetermined temperature value, on one or more blocks on which data was written at a temperature lower than the predetermined temperature value.

    ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE
    27.
    发明公开
    ADAPTIVE ENHANCED CORRECTIVE READ BASED ON WRITE AND READ TEMPERATURE 审中-公开

    公开(公告)号：US20230393776A1

    公开(公告)日：2023-12-07

    申请号：US17830625

    申请日：2022-06-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhenming Zhou ,  Murong Lang ,  Ching-Huang Lu ,  Nagendra Prasad Ganesh Rao

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/0652

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

    UNSELECTED SUB-BLOCK SOURCE LINE AND BIT LINE PRE-CHARGING TO REDUCE READ DISTURB
    28.
    发明申请
    UNSELECTED SUB-BLOCK SOURCE LINE AND BIT LINE PRE-CHARGING TO REDUCE READ DISTURB 有权

    公开(公告)号：US20230024346A1

    公开(公告)日：2023-01-26

    申请号：US17591361

    申请日：2022-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Xiangyu Yang ,  Hong-Yan Chen ,  Ching-Huang Lu

    IPC: G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/30

    Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

    EARLY DISCHARGE SEQUENCES DURING READ RECOVERY TO ALLEVIATE LATENT READ DISTURB
    29.
    发明申请
    EARLY DISCHARGE SEQUENCES DURING READ RECOVERY TO ALLEVIATE LATENT READ DISTURB 有权

    公开(公告)号：US20220392530A1

    公开(公告)日：2022-12-08

    申请号：US17540752

    申请日：2021-12-02

    Applicant: Micron Technology, Inc.

    Inventor： Xiangyu Yang ,  Ching-Huang Lu

    IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

    Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including initiating a read recovery process associated with a block of the memory array. The block includes wordlines at an initial voltage. The operations further include causing an early discharge sequence to be performed on a first set of wordlines of the wordlines during the read recovery process to alleviate latent read disturb. The early discharge sequence includes ramping the first set of wordlines from the initial voltage to a ramping voltage while maintaining a second set of wordlines of the wordlines at the initial voltage.

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